公开(公告)号：US20240172428A1

公开(公告)日：2024-05-23

申请号：US18518293

申请日：2023-11-22

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： KYUNGHWAN KIM ,  Hyungeun Choi ,  Keunnam Kim ,  Seokhan Park ,  Seokho Shin ,  Joongchan Shin ,  Kiseok Lee ,  Sangho Lee ,  Moonyoung Jeong

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315

Abstract: A semiconductor device is provided. The semiconductor device includes: a lower structure including a bit line; a cell semiconductor body vertically overlapping the bit line, on the lower structure; a peripheral semiconductor body including a portion disposed on a same level as at least a portion of the cell semiconductor body, on the lower structure; and a peripheral gate on the peripheral semiconductor body, wherein the peripheral semiconductor body includes a lower region having a first width and an upper region having a second width, greater than the first width on the lower region.

公开(公告)号：US20240357801A1

公开(公告)日：2024-10-24

申请号：US18530342

申请日：2023-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanjin Lim ,  Jinwoo Han ,  Kiseok Lee ,  Keunnam Kim ,  Seokhan Park ,  Moonyoung Jeong

IPC: H10B12/00 ,  H01L21/28 ,  H01L29/51

CPC classification number: H10B12/482 ,  H01L29/40111 ,  H01L29/516 ,  H10B12/315 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor memory device includes a bit line extending in a first direction, an active pattern on the bit line, the active pattern including first and second vertical portions facing each other in the first direction and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion between the first and second vertical portions, the first and second word lines extending in a second direction crossing the first direction, a gate insulating pattern between the first and second word lines and the active pattern, and a capacitor connected to each of the first and second vertical portions, the capacitor including a first electrode pattern connected to one of the first and second vertical portions, a second electrode pattern on the first electrode pattern, and a ferroelectric pattern between the first electrode pattern and the second electrode pattern.

公开(公告)号：US20220262731A1

公开(公告)日：2022-08-18

申请号：US17487460

申请日：2021-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Hyunseo Shin ,  Seokhan Park ,  Seunghune Yang

IPC: H01L23/528 ,  H01L27/108

Abstract: A semiconductor device may include a gate structure, first and second source/drain layers, first and second contact plugs, first and second conductive structures, and a third contact plug. The gate structure may be on a substrate. The first and second source/drain layers may be at upper portions, respectively, of the substrate on opposite sidewalls of the gate structure and adjacent thereto. The first and second contact plugs may be on the first and second source/drain layers, respectively, and each contact plugs may extend in a vertical direction. The first and second conductive structures may contact upper surfaces of the first and second contact plugs, respectively. The third contact plug may contact an upper surface of the second conductive structure. A height and a width of the second conductive structure may be greater than a height and a width of the first conductive structure.

公开(公告)号：US11322544B2

公开(公告)日：2022-05-03

申请号：US16734937

申请日：2020-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Taehun Kim ,  Seokhan Park ,  Satoru Yamada ,  Jaeho Hong

IPC: H01L27/24 ,  G11C16/10 ,  G11C16/26 ,  G11C13/00 ,  H01L45/00 ,  H01L27/11524 ,  H01L27/1157

Abstract: A vertical semiconductor device includes: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and gate patterns on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate.

公开(公告)号：US20250157925A1

公开(公告)日：2025-05-15

申请号：US18675252

申请日：2024-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun Choi ,  Jinwoo Han ,  Seokhan Park

IPC: H01L23/528 ,  H10B12/00

Abstract: A semiconductor device includes: a substrate including a memory cell region and a contact region; active layers extending in a first horizontal direction and stacked to be spaced apart from each other in a vertical direction on the memory cell region; gate electrodes disposed between the active layers, extending in a second horizontal direction, and stacked to be spaced apart from each other in the vertical direction; connecting conductive lines extending in the first horizontal direction and stacked to be spaced apart from each other in the vertical direction, on the contact region; and vertical conductive patterns extending in the vertical direction and in contact with the active layers, on the memory cell region. Each of the connecting conductive lines are disposed on the same level, among the gate electrodes, and are in contact with the gate electrodes spaced apart from each other in the first horizontal direction.

公开(公告)号：US20250133728A1

公开(公告)日：2025-04-24

申请号：US18825982

申请日：2024-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Iljae Shin ,  Jinwoo Han ,  Seokhan Park ,  Sungmin Park ,  Gyuhwan Oh ,  Kiseok Lee

IPC: H10B12/00 ,  H01L29/45

Abstract: A semiconductor device includes a bit line, a channel, a word line and a capacitor. The bit line is disposed on a substrate, and extends in a first direction substantially perpendicular to an upper surface of the substrate. The channel at least partially surrounds a sidewall of the bit line. The word line is disposed on the substrate, and at least a portion of the word line overlaps the channel in a horizontal direction substantially parallel to the upper surface of the substrate. The capacitor is electrically connected to the channel, and at least a portion of the capacitor overlaps the channel and the word line in the horizontal direction.

公开(公告)号：US20240074155A1

公开(公告)日：2024-02-29

申请号：US18236143

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyuk Kim ,  Taegyu Kang ,  Seokho Shin ,  Kiseok Lee ,  Sangho Lee ,  Keunnam Kim ,  Seokhan Park ,  Joongchan Shin ,  Moonyoung Jeong ,  Eunju Cho

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor device includes a substrate, a bit line extending on the substrate in a first direction, first and second active patterns on the bit line, a back-gate electrode between the first and second active patterns and extending across the bit line and in a second direction that is perpendicular to the first direction, a first word line extending in the second direction at one side of the first active pattern, a second word line extending in the second direction at the other side of the second active pattern, and a contact pattern connected to each of the first and second active patterns, wherein the contact pattern sequentially includes an epitaxial growth layer, a doped polysilicon layer, and a silicide layer.

公开(公告)号：US11569239B2

公开(公告)日：2023-01-31

申请号：US17126195

申请日：2020-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Bong-Soo Kim ,  Jiyoung Kim ,  Hui-Jung Kim ,  Seokhan Park ,  Hunkook Lee ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10 ,  H01L23/522 ,  H01L49/02

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

公开(公告)号：US20190088739A1

公开(公告)日：2019-03-21

申请号：US15890707

申请日：2018-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Myeong-Dong Lee ,  Hui-Jung Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Seokhan Park ,  Woosong Ahn ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L29/06 ,  H01L27/108 ,  H01L23/528 ,  H01L23/535

Abstract: A semiconductor memory device includes a substrate including active regions, word lines in the substrate and each extending in a first direction parallel to an upper surface of the substrate, bit line structures connected to the active regions, respectively, and each extending in a second direction crossing the first direction, and spacer structures on sidewalls of respective ones of the bit line structures. Each of the spacer structures includes a first spacer, a second spacer, and a third spacer. The second spacer is disposed between the first spacer and the third spacer and includes a void defined by an inner surface of the second spacer. A height of the second spacer is greater than a height of the void.

公开(公告)号：US20250081514A1

公开(公告)日：2025-03-06

申请号：US18650251

申请日：2024-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuhwan Oh ,  Seokhan Park ,  Bowon Yoo ,  Jinwoo Han

IPC: H01L29/78 ,  H01L29/10 ,  H10B12/00

Abstract: A semiconductor device includes a back gate line that is on a substrate and extends in a first direction, a plurality of channel structures that are on side walls of the back gate line and spaced apart from each other in a second first direction that intersects the first direction, a word line that at least partially surrounds the plurality of channel structures, and a bit line on a lower surface of each of the plurality of channel structures, where each of the plurality of channel structures includes: a first side wall facing the word line, and a second side wall that faces the back gate line and contacts an edge of the first side wall, where the first side wall is curved, and where the second side wall is flat.