公开(公告)号：US20180197988A1

公开(公告)日：2018-07-12

申请号：US15400244

申请日：2017-01-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Perumal RATNAM ,  Christopher PETTI ,  Juan SAENZ ,  Guangle ZHOU ,  Abhijit BANDYOPADHYAY ,  Tanmay KUMAR

IPC: H01L29/78 ,  H01L29/423 ,  H01L23/528 ,  H01L27/24 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L23/5283 ,  H01L27/2454 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/78648

Abstract: A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.

公开(公告)号：US20190097132A1

公开(公告)日：2019-03-28

申请号：US15714246

申请日：2017-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bijesh RAJAMOHANAN ,  Juan SAENZ

IPC: H01L45/00 ,  H01L27/112 ,  H01L29/10

Abstract: A method of operating a resistive memory device includes providing a resistive memory device including an array of resistive memory cells, where each of the resistive memory cells includes a resistive memory material having at least two different resistive states, performing a first mode read operation on a group of resistive memory cells within the array, determining a bit error rate for data generated by the first mode read operation, determining whether the determined bit error rate is below a predetermined limit, and performing a second mode read operation on the group of resistive memory cells within the array based on a threshold voltage if the determined bit error rate is above the predetermined limit.