公开(公告)号：US11343454B2

公开(公告)日：2022-05-24

申请号：US16854057

申请日：2020-04-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Roger Panicacci ,  Tim W. Chan

IPC: H04N5/372 ,  H01L27/146 ,  H04N5/369 ,  H04N5/347 ,  H04N5/355 ,  H04N5/225 ,  H04N5/232

Abstract: Imaging circuitry may include circuits for implementing feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using variable charge integration times, variable resistors in the readout path, and/or variable switch on times in the readout path. The weighted pixels values may be binned and combined to obtain an output neuron voltage for at least one layer in a neural network. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.