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公开(公告)号：US20210334009A1
公开(公告)日：2021-10-28
申请号：US17011300
申请日：2020-09-03
Applicant: SK hynix Inc.
Inventor： In JUNG
IPC: G06F3/06 , G06F12/1009 , G06F12/0802
Abstract: The present disclosure includes a memory system, a memory controller, and an operation method thereof. The memory system may cache a subset of all map segments in a mapping table indicating mapping information between logical addresses and physical addresses in a map cache, may select map segments on which locking is to be set from the map segments cached in the map cache so as not to be evicted from the map cache based on information on all commands received from a host during a set period of time, and may set lock flags for the map segments on which locking is to be set. Accordingly, the memory system may reduce the overhead occurring in reloading previously evicted map segments in the process of updating a mapping table, and may optimize update performance for a mapping table within a limit that guarantees caching performance to a predetermined level or higher.
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公开(公告)号：US20210109675A1
公开(公告)日：2021-04-15
申请号：US16822332
申请日：2020-03-18
Applicant: SK hynix Inc.
Inventor： In JUNG
IPC: G06F3/06 , G06F12/1009
Abstract: A memory system, a memory controller and an operating method are disclosed. In a write operation of first data into a superblock, depending on a read count value of a first memory block among a plurality of memory blocks in a memory device, the write operation of the first data is controlled to be performed one of the first memory block and a second memory block among the plurality of memory blocks. As a consequence, read count values in the memory device may be distributed, and the usage rate of the memory blocks may be increased, whereby it is possible to efficiently utilize a storage space.
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公开(公告)号：US20190095139A1
公开(公告)日：2019-03-28
申请号：US16188896
申请日：2018-11-13
Applicant: SK hynix Inc.
Inventor： In JUNG , Soo Nyun KIM
Abstract: A memory system includes: a flash translation layer block suitable for receiving data from a host and converting a logic address into a physical address to store address information, during a write operation;a first buffer unit suitable for sequentially receiving the data from the flash translation layer; and a second buffer unit suitable for randomly receiving the data from the flash translation layer, wherein the flash translation layer block outputs data to only one of the first and second buffer units in a fast write mode during the write operation, and updates mapping information on the data stored in the one of the first and second buffer units after the fast write mode is terminated.
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公开(公告)号：US20190227931A1
公开(公告)日：2019-07-25
申请号：US16110503
申请日：2018-08-23
Applicant: SK hynix Inc.
Inventor： In JUNG
IPC: G06F12/0811 , G06F12/1009
Abstract: A data storage device may include: a nonvolatile memory device including first and second memory regions configured to be read-interleaved with each other; and a processor configured to select a first read command among read commands received from a host device, select a second read command among the read commands excluding the first read command, and control the nonvolatile memory device to perform map read on the first and second read commands at the same time. The processor selects, as the second read command, at least one read command that is configured to be read-interleaved with the first read command.
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Patent Agency Ranking
公开(公告)号：US20200150898A1
公开(公告)日：2020-05-14
申请号：US16231880
申请日：2018-12-24
Applicant: SK hynix Inc.
Inventor： Eu Joon BYUN , Byung Jun KIM , In JUNG , Seung Ho CHOI
Abstract: Provided is an operating method of a memory system which includes a plurality of nonvolatile memory devices; and a controller configured to control the nonvolatile memory devices to store data therein. The operating method may include: receiving, by the controller, a write request for logical addresses from a host device; determining, by the controller, whether a start logical address among the logical addresses satisfies an alignment condition, the start logical address indicating where a write operation is to be performed in a target nonvolatile memory device among the nonvolatile memory devices; determining, by the controller, target data by determining one or more target logical addresses among the logical addresses through an alignment operation, when the start logical address does not satisfy the alignment condition; and controlling, by the controller, the target nonvolatile memory device to perform the write operation on the target data.
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公开(公告)号：US20190227719A1
公开(公告)日：2019-07-25
申请号：US16103413
申请日：2018-08-14
Applicant: SK hynix Inc.
Abstract: The storage device includes a memory device including a plurality of planes, and a memory controller configured to store, while the memory device is in a busy state, read requests for different planes among read requests for the memory device as read requests to be processed by the memory device after the busy state of the memory device is terminated.
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公开(公告)号：US20190220416A1
公开(公告)日：2019-07-18
申请号：US16110420
申请日：2018-08-23
Applicant: SK hynix Inc.
Inventor： In JUNG , Byeong Gyu PARK , Young Ick CHO
IPC: G06F12/1009
Abstract: A data storage apparatus includes a nonvolatile memory device including block groups, a random access memory including a sequential map table that stores a sequential map entry for consecutive sequential write logical addresses, among write addresses received from a host apparatus, greater than or equal to a predetermined threshold number, and a processor configured to determine whether or not first sequential write logical addresses are present among logical addresses corresponding to physical addresses for a first region of a first block group when a write operation for the first region of the first block group in response to a write request received from the host apparatus is completed, generate a first sequential map entry for the first sequential write logical addresses when the first sequential write logical addresses are present, and store the first sequential map entry in the sequential map table.
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公开(公告)号：US20160283395A1
公开(公告)日：2016-09-29
申请号：US14835369
申请日：2015-08-25
Applicant: SK hynix Inc.
Inventor： In JUNG , Soo Nyun KIM
CPC classification number: G06F3/0679 , G06F3/0613 , G06F3/0656 , G06F12/0246 , G06F2212/1016 , G06F2212/7201 , G06F2212/7203
Abstract: A memory system includes: a flash translation layer block suitable for receiving data from a host and converting a logic address into a physical address to store address information, during a write operation;a first buffer unit suitable for sequentially receiving the data from the flash translation layer; and a second buffer unit suitable for randomly receiving the data from the flash translation layer, wherein the flash translation layer block outputs data to only one of the first and second buffer units in a fast write mode during the write operation, and updates mapping information on the data stored in the one of the first and second buffer units after the fast write mode is terminated.
Abstract translation: 第一缓冲单元，适于顺序地从闪存转换层接收数据; 以及适用于从闪存转换层中随机接收数据的第二缓冲器单元，其中闪存转换层块在写入操作期间以快速写入模式仅向第一和第二缓冲器单元之一输出数据，并且更新映射信息 在快速写入模式之后存储在第一和第二缓冲器单元之一中的数据被终止。
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公开(公告)号：US20210334218A1
公开(公告)日：2021-10-28
申请号：US17012735
申请日：2020-09-04
Applicant: SK hynix Inc.
Inventor： In JUNG
IPC: G06F12/109 , G06F12/0875
Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method of a memory system. According to embodiments of the present disclosure, the memory system, before updating a mapping table which includes mapping information between logical addresses and physical addresses, may assign a portion of a map cache area for caching a plurality of map segments in the mapping table as a map update area for updating the mapping table, and may load a subset of the plurality of map segments to the map update area. Accordingly, it is possible to quickly update a mapping table and to optimize update performance for a mapping table within a limit that guarantees caching performance to a predetermined level or higher.
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