公开(公告)号：US20220028806A1

公开(公告)日：2022-01-27

申请号：US17498177

申请日：2021-10-11

Applicant: SK hynix Inc.

Inventor： Jae Hoon LEE ,  Hyung Ho CHO

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a substrate and a semiconductor chip disposed over the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper ground electrode plate disposed over the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface which is surrounded by the upper ground electrode plate and is spaced apart from the upper ground electrode plate with an insulating material between the dummy power pattern and the upper ground electrode plate. A ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.

公开(公告)号：US20200286856A1

公开(公告)日：2020-09-10

申请号：US16591072

申请日：2019-10-02

Applicant: SK hynix Inc.

Inventor： Jae Hoon LEE ,  Ji Yeong YOON

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate having a hole pattern including a first through hole extending in a first direction and a second through hole extending in a second direction substantially perpendicular to the first direction, at least one first semiconductor chip disposed on the package substrate to overlap with the first through hole, at least one second semiconductor chip disposed on the package substrate to overlap with the second through hole, first bonding wires passing through the first through hole to electrically connect the at least one first semiconductor chip to the package substrate, and second bonding wires passing through the second through hole to electrically connect the at least one second semiconductor chip to the package substrate.

公开(公告)号：US20200176406A1

公开(公告)日：2020-06-04

申请号：US16539602

申请日：2019-08-13

Applicant: SK hynix Inc.

Inventor： Jae Hoon LEE ,  Sun Kyu KONG ,  Ji Yeong YOON

IPC: H01L23/00 ,  H01L23/522

Abstract: A package substrate of a semiconductor package includes second and third pad bonding portions respectively located at both sides of a first pad bonding portion disposed on a substrate body. First to third via landing portions are disposed to be spaced apart from the first to third pad bonding portions. First and second connection trace portions are disposed to be parallel with each other, and a first guard trace portion is disposed to be substantially parallel with the first connection trace portion. The second connection trace portion is connected to the first guard trace portion through a first connection plane portion, and the first connection plane portion connects the second connection trace portion to the second via landing portion. The third pad bonding portion is connected to the third via landing portion through a second connection plane portion.

公开(公告)号：US20210167017A1

公开(公告)日：2021-06-03

申请号：US16900342

申请日：2020-06-12

Applicant: SK hynix Inc.

Inventor： Ju Il EOM ,  Jae Hoon LEE

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a lower chip, an interposer, and an upper chip which are stacked on the package substrate, and bonding wires electrically connecting the lower chip to the package substrate. The lower chip includes first and second lower chip pads spaced apart from each other on an upper surface of the lower chip, wire bonding pads bonded to the bonding wires on the upper surface of the lower chip, and lower chip redistribution lines electrically connecting the second lower chip pad to the wire bonding pad. The interposer includes an upper chip connection pad on an upper surface of the interposer, a lower chip connection pad on a lower surface of the interposer, and a through via electrode electrically connecting the upper chip connection pad to the lower chip connection pad.

公开(公告)号：US20190333899A1

公开(公告)日：2019-10-31

申请号：US16184741

申请日：2018-11-08

Applicant: SK hynix Inc.

Inventor： Juil EOM ,  Bok Kyu CHOI ,  Jae Hoon LEE ,  Jin Woo PARK

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/31

Abstract: A stack package includes a first sub-package and a second sub-package stacked on the first sub-package. The first sub-package includes a first through mold via (TMV) for connection spaced apart from a first semiconductor chip in an X-axis direction, a first TMV for bypass spaced apart from the first semiconductor chip in a Y-axis direction, and a first redistribution line (RDL) pattern connecting the first semiconductor chip to the first TMV for connection. The second sub-package includes a second TMV for connection spaced apart from a second semiconductor chip in the Y-axis direction and another RDL pattern connecting the second semiconductor chip to the second TMV for connection. the second sub-package is stacked on the first sub-package such that the second TMV for connection is connected to the first TMV for bypass.

公开(公告)号：US20190333894A1

公开(公告)日：2019-10-31

申请号：US16183556

申请日：2018-11-07

Applicant: SK hynix Inc.

Inventor： Juil EOM ,  Jae Hoon LEE ,  Bok Kyu CHOI

IPC: H01L25/065 ,  H01L23/498

Abstract: A stack package includes a first sub-package and a second sub-package stacked on the first sub-package. The first sub-package includes a first semiconductor chip, a first through mold via (TMV) for connection that is spaced apart from the first semiconductor chip in an X-axis direction, a first TMV for bypass that is spaced apart from the first semiconductor chip in a Y-axis direction, and a redistribution line (RDL) pattern for connecting the first semiconductor chip to the first TMV for connection. The second sub-package includes a second semiconductor chip, a second TMV for connection that is spaced apart from the second semiconductor chip in the Y-axis direction, and another RDL pattern for connecting the second semiconductor chip to the second TMV for connection. The second sub-package stacked is stacked on the first sub-package such that the second TMV for connection is connected to the first TMV for bypass.

公开(公告)号：US20180138150A1

公开(公告)日：2018-05-17

申请号：US15443509

申请日：2017-02-27

Applicant: SK hynix Inc.

Inventor： Ju Il EOM ,  Jae Hoon LEE ,  Sang Joon LIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/06137 ,  H01L2224/06177 ,  H01L2224/0912 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/17104 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/06135 ,  H01L2224/06136

Abstract: A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. The first and second semiconductor chips are stacked such that the first and second active surfaces face each other.

公开(公告)号：US20240196515A1

公开(公告)日：2024-06-13

申请号：US18306874

申请日：2023-04-25

Applicant: SK hynix Inc.

Inventor： Jae Hoon LEE ,  Jong Wook KIM ,  Ju Il EOM

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11

CPC classification number: H05K1/0213 ,  H05K1/09 ,  H05K1/111 ,  H05K1/115 ,  H05K2201/0776

Abstract: A substrate in accordance with an embodiment of the disclosure includes a signal transmission layer including a signal transmission pad and a signal transmission interconnection; a first dielectric layer stacked on the signal transmission layer; and a first reference voltage layer stacked on the first dielectric layer. The first reference voltage layer includes a first space hole and an impedance calibrator. The impedance calibrator includes an impedance calibration part disposed in the first space hole; and a first bridge connecting a first portion of the impedance calibration part to a first portion of the first reference voltage layer.

公开(公告)号：US20210327830A1

公开(公告)日：2021-10-21

申请号：US16924836

申请日：2020-07-09

Applicant: SK hynix Inc.

Inventor： Jae Hoon LEE ,  Hyung Ho CHO

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a substrate and a semiconductor chip disposed over the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper ground electrode plate disposed over the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface which is surrounded by the upper ground electrode plate and is spaced apart from the upper ground electrode plate with an insulating material between the dummy power pattern and the upper ground electrode plate. A ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.

公开(公告)号：US20200176407A1

公开(公告)日：2020-06-04

申请号：US16540940

申请日：2019-08-14

Applicant: SK hynix Inc.

Inventor： Jae Hoon LEE ,  Ju Il EOM

IPC: H01L23/00 ,  H01L23/522

Abstract: A package substrate of a semiconductor package includes second and third pad bonding portions respectively located at both sides of a first pad bonding portion on a substrate body. First to third via landing portions are spaced apart from the first to third pad bonding portions. First and second connection trace portions are disposed side by side. A first guard trace portion is substantially parallel with the first connection trace portion. The second connection trace portion is connected to the first guard trace portion through a first connection plane portion. The first connection plane portion connects the second connection trace portion to the second via landing portion. The third pad bonding portion is connected to the third via landing portion through a second connection plane portion. A semiconductor chip mounted on the package substrate includes first inner chip pads and first outer chip pads bonded to the package substrate.