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公开(公告)号：US20170358881A1
公开(公告)日：2017-12-14
申请号：US15617735
申请日：2017-06-08
Applicant: TE CONNECTIVITY CORPORATION
Inventor： GRAHAM HARRY SMITH, JR. , SCOTT ERIC WALTON , MICHAEL FRANK CINA
CPC classification number: H01R12/721 , H01P5/028 , H01R13/112 , H05K1/025 , H05K1/0251 , H05K1/115 , H05K1/117 , H05K2201/0776 , H05K2201/09381 , H05K2201/09481 , H05K2201/09618 , H05K2201/09672 , H05K2201/09727 , H05K2201/0979
Abstract: An electrical contact pad for electrically contacting a connector includes first, second and third regions. The first region is connected to a trace. The second region is adjacent to the first region and has a width less than the first region. The third region is adjacent to the second region and has a width that is greater than the second region. The third region is sized to make contact with a connector. Having the width of the second region be smaller than the width of the first and third regions increases an impedance of the electrical contact pad.
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公开(公告)号：US11937368B2
公开(公告)日：2024-03-19
申请号：US17222185
申请日：2021-04-05
Applicant: OpenLight Photonics, Inc.
Inventor： Christopher Paul Wyland
CPC classification number: H05K1/0251 , H05K1/115 , H05K3/4038 , H05K3/46 , H05K2201/0776 , H05K2201/093
Abstract: Described are various configurations of high-speed via structures. Various embodiments can reduce or entirely eliminate insertion loss in high-speed signal processing environments by using impedance compensation structures that decrease a mismatch in components of a circuit. An impedance compensation structure can include a metallic structure placed near a via to lower an impedance difference between the via and a conductive pathway connected to the via.
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3.发明申请公开(公告)号：US20170245366A1
公开(公告)日：2017-08-24
申请号：US15222969
申请日：2016-07-29
Applicant: Wistron NeWeb Corp.
Inventor： Cheng-Hsien Hsu , Chih-Yuan Chiang , Cheng-Huang Chen
CPC classification number: H05K1/144 , G01R31/2812 , G01R31/2818 , H05K1/0268 , H05K1/11 , H05K2201/042 , H05K2201/0776
Abstract: A dual printed circuit board assembly, a printed circuit board, and a modular printed circuit board are provided. The printed circuit board includes a plurality of first connection points. The modular printed circuit board includes a plurality of second connection points. The modular printed circuit board is adapted to be mounted on the printed circuit board and includes a sensing unit, a first detecting unit, and a first notifying unit. The sensing unit outputs a detecting voltage according to a contact state between the first connection points and the second connection points. The first detecting unit determines whether the first connection points are respectively connected to the corresponding second connection points according to the detecting voltage. When one of the first connection points is not connected to the corresponding one of the second connection points, the first detecting unit controls the first notifying unit to issue a notification.
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公开(公告)号：US20150313005A1
公开(公告)日：2015-10-29
申请号：US14406913
申请日：2012-06-15
Applicant: Masashi TAKABATAKE , Kenji KASHIWAGI
Inventor： Masashi TAKABATAKE , Kenji KASHIWAGI
CPC classification number: H05K1/0213 , H05K1/025 , H05K1/0253 , H05K1/111 , H05K3/3421 , H05K2201/0776 , H05K2201/09372 , H05K2201/0969 , H05K2201/10189 , Y02P70/611
Abstract: [Object] There is suggested a printed circuit board capable of realizing impedance matching by securing joint reliability between signal pins of a surface mount connector and signal pin pads and preventing the reduction of impedance of signal pin pads while minimizing the reduction of a wirable area.[Solution] A printed circuit board equipped with a signal pin pad, which is soldered to a signal pin from a surface mount connector, and a ground layer located as a lower layer below the signal pin pad; wherein a fillet is formed around a joint area between the signal pin and the signal pin pad after soldering; wherein a cut-out portion is provided in the signal pin pad within a joint area with the signal pin; and wherein the size of the cut-out portion is set within the range of being completely covered within the joint area with the signal pin based on size tolerance of the signal pin, fabrication tolerance of the printed circuit board, and mount position tolerance of the surface mount connector.
Abstract translation: 提出了一种印刷电路板，其能够通过确保表面安装连接器的信号引脚和信号引脚焊盘之间的连接可靠性来实现阻抗匹配，并且防止信号引脚焊盘的阻抗减小，同时最小化可吸收区域的减少。 [解决方案]配备有从表面安装连接器焊接到信号引脚的信号引脚焊盘的印刷电路板和位于信号引脚焊盘下方的下层的接地层; 其中在焊接之后，在信号引脚和信号引脚焊盘之间的接合区域周围形成圆角; 其中在与所述信号引脚的接合区域内的所述信号引脚焊盘中设置切口部分; 并且其中，根据信号引脚的尺寸公差，印刷电路板的制造公差以及印刷电路板的安装位置公差，将切除部分的尺寸设定在与信号销的接合区域内完全覆盖的范围内 表面贴装连接器。
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公开(公告)号：US20240179831A1
公开(公告)日：2024-05-30
申请号：US18515661
申请日：2023-11-21
Applicant: CANON KABUSHIKI KAISHA
Inventor： HIROYUKI YAMAGUCHI , MOMOKA UMEGAE
CPC classification number: H05K1/0262 , H05K1/112 , H04N25/709 , H05K2201/0335 , H05K2201/0776
Abstract: An electronic module includes a plurality of loads, a first wiring portion, a second wiring portion, a power source unit, and a feedback portion. The first wiring portion includes a plurality of first portions to which the plurality of loads are respectively connected, and a plurality of second portions each closest to a corresponding one of the plurality of first portions. The second wiring portion is connected to the plurality of second portions. The power source unit includes a feedback terminal, an output terminal, and a power source circuit. In the first wiring portion, a minimum path length from each of the plurality of second portions to the corresponding one of the plurality of first portions is smaller than 1/2 of a minimum path length from a part of the first wiring portion connected to the output terminal to the corresponding one of the plurality of first portions.
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Patent Agency Ranking
公开(公告)号：US20240074054A1
公开(公告)日：2024-02-29
申请号：US17895247
申请日：2022-08-25
Applicant: The Phoenix Company of Chicago, Inc.
Inventor： Salvatore J. Gullotta, SR. , Sri Satya Parthiva Sumanam
CPC classification number: H05K1/115 , H05K1/0296 , H05K2201/0776
Abstract: Vertical launch impedance matched through-hole vias to ensure proper impedance matching is maintained after a printed circuit board connector is attached to a printed circuit board. A conductive via having a center aperture and a via body having a slot adjacent either the via top surface and/or via bottom surface, and a dielectric component insertable within the via center aperture, and having a slot aligned with the conductive via body slot. The dielectric component having a center aperture with a conductive member in electrical communication with a PCB signal trace without contact to the conductive via. A printed circuit board connector having a center signal pin with a slotted dielectric component attached thereto, or a slotted dielectric component in conjunction with a slotted, conductive via body attached thereto.
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公开(公告)号：US20180192517A1
公开(公告)日：2018-07-05
申请号：US15854598
申请日：2017-12-26
Applicant: Micron Technology, Inc.
Inventor： Atsushi Morishima
CPC classification number: H05K1/115 , H05K1/025 , H05K1/114 , H05K1/181 , H05K2201/0776 , H05K2201/09227 , H05K2201/09309 , H05K2201/09609 , H05K2201/0979
Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.
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公开(公告)号：US09888574B1
公开(公告)日：2018-02-06
申请号：US15399664
申请日：2017-01-05
Applicant: Micron Technology, Inc.
Inventor： Atsushi Morishima
CPC classification number: H05K1/115 , H05K1/025 , H05K1/114 , H05K1/181 , H05K2201/0776 , H05K2201/09227 , H05K2201/09309 , H05K2201/09609 , H05K2201/0979
Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.
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9.发明申请公开(公告)号：US20160192477A1
公开(公告)日：2016-06-30
申请号：US14902980
申请日：2014-07-07
Applicant: INKTEC Co., Ltd.
Inventor： Kwang-Choon Chung , Ji Hoon Yoo , Joonki Seong , Byung Hun Kim , Nam Boo Cho , Myung-Bong Yoo
CPC classification number: H05K1/0274 , G06F3/041 , G06F2203/04103 , H01L51/445 , H05K1/0213 , H05K1/0289 , H05K1/0298 , H05K1/0306 , H05K1/032 , H05K1/034 , H05K1/0346 , H05K1/097 , H05K3/0026 , H05K3/06 , H05K3/067 , H05K3/12 , H05K3/1258 , H05K2201/0776 , Y02E10/549 , Y02P70/521
Abstract: Provided herein is a method for manufacturing a conductive transparent substrate, the method including forming a plurality of main electrodes on the substrate such that the main electrodes are distanced from one another; and forming a connecting electrode that electrically connects two or more main electrodes such that the plurality of main electrodes are grouped into a plurality of group electrodes that are electrically disconnected from one another, thereby producing a conductive transparent substrate with excellent transmittance in a process of high yield.
Abstract translation: 本发明提供一种制造导电透明基板的方法，该方法包括在基板上形成多个主电极，使得主电极彼此间隔开; 以及形成连接两个或多个主电极的连接电极，使得所述多个主电极被分组成彼此电断开的多个组电极，从而在高过程中产生具有优异透射率的导电透明基板 产量。
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公开(公告)号：US20240215150A1
公开(公告)日：2024-06-27
申请号：US18423227
申请日：2024-01-25
Inventor： CHUN-WEI CHANG , JIAN-HONG LIN , SHU-YUAN KU , WEI-CHENG LIU , YINLUNG LU , JUN HE
CPC classification number: H05K1/0242 , H05K1/0251 , H05K1/116 , H05K3/427 , H05K3/429 , H05K2201/0776
Abstract: A package component includes a first substrate and a first conductive layer. The first substrate has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed over the first surface of the first substrate. The first conductive layer includes a first conductive feature and a second conductive feature over the first conductive feature. The second conductive features covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the second conductive feature. The first substrate includes a single-sided or a double-sided copper-clad laminate.
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