公开(公告)号：US20240395746A1

公开(公告)日：2024-11-28

申请号：US18497654

申请日：2023-10-30

Applicant: SK hynix Inc.

Inventor： Jae Jun LEE ,  Sung Kyu KIM ,  Jong Yeon KIM ,  Ki Ill MOON ,  Mi Seon LEE

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/552

Abstract: In an embodiment, a semiconductor die includes a substrate, an interlayer insulating layer under a front-side surface the substrate, a horizontal metal interconnection in the interlayer insulating layer, a front-side pad under a lower surface of the interlayer insulating layer, a front-side bump structure under a lower surface of the front-side pad, a through-electrode vertically passing through the substrate, a back-side insulating layer over the back-side surface of the substrate, a first back-side metal plate layer over the back-side insulating layer, a back-side passivation layer over the back-side insulating layer and covering the first back-side metal plate layer, and a back-side bump structure over the through-electrode and the back-side passivation layer.

公开(公告)号：US20250167123A1

公开(公告)日：2025-05-22

申请号：US19035040

申请日：2025-01-23

Applicant: SK hynix Inc.

Inventor： Jae Jun LEE ,  Sung Kyu KIM ,  Jong Yeon KIM ,  Ki Ill MOON ,  Ju Heon YANG ,  BEOLI OK

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065

Abstract: A semiconductor die includes interlayer insulating layer, a signal horizontal metal interconnection and a power horizontal metal interconnection, a front-side passivation layer, a signal front-side bump structure and a power front-side bump structure, a signal vertical via plug, and a power vertical via plug over a front-side of a substrate; and a back-side insulating layer, a back-side metal plate layer, a back-side passivation layer, a signal back-side bump structure and a power back-side bump structure, a signal through-electrode, and a power through-electrode over a back-side of the substrate. Upper ends of the signal through-electrode and the power through-electrode protrude from the back-side surface of the substrate. The back-side metal plate layer is not to be electrically connected to the signal through-electrode. The back-side metal plate layer is electrically connected to the power bump structure.

公开(公告)号：US20240105656A1

公开(公告)日：2024-03-28

申请号：US18186284

申请日：2023-03-20

Applicant: SK hynix Inc.

Inventor： Jae Jun LEE ,  Jong Yeon KIM ,  Jong Hoon KIM ,  Ju Heon YANG ,  Mi Seon LEE

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L21/485 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/113 ,  H01L2224/13007 ,  H01L2224/13582 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2924/384

Abstract: A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.