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    SEMICONDUCTOR DEVICES INCLUDING SUBSTRATES BONDED TO EACH OTHER AND METHODS FOR FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING SUBSTRATES BONDED TO EACH OTHER AND METHODS FOR FABRICATING THE SAME 有权

    公开(公告)号：US20230120361A1

    公开(公告)日：2023-04-20

    申请号：US17689419

    申请日：2022-03-08

    Applicant: SK hynix Inc.

    Inventor： Mi Seon LEE ,  Sung Kyu KIM ,  Jong Hoon KIM

    IPC: H01L23/48 ,  H01L23/532 ,  H01L23/00

    Abstract: There are provided a semiconductor and a method of fabricating the same. The semiconductor device may include a second semiconductor substrate directly bonded to a first semiconductor substrate. The first semiconductor substrate may include a first through via with an end portion protruding through a first top surface, the first top surface being a top surface of a first semiconductor substrate body, a liner extending to partially expose a side surface of the end portion of the first through via, and a first diffusion barrier layer. The liner may include a third top surface that is positioned at a lower height than a second top surface, the second top surface being a top surface of the end portion of the first through via and substantially equal to the first top surface. Alternatively, the liner may include a third surface positioned at a height that is lower than the second top surface and higher than the first top surface.

    SEMICONDUCTOR DIE, A SEMICONDUCTOR DIE STACK, A SEMICONDUCTOR MODULE, AND METHODS OF FORMING THE SEMICONDUCTOR DIE AND THE SEMICONDUCTOR DIE STACK
    6.
    发明申请
    SEMICONDUCTOR DIE, A SEMICONDUCTOR DIE STACK, A SEMICONDUCTOR MODULE, AND METHODS OF FORMING THE SEMICONDUCTOR DIE AND THE SEMICONDUCTOR DIE STACK 有权

    公开(公告)号：US20230139612A1

    公开(公告)日：2023-05-04

    申请号：US17697708

    申请日：2022-03-17

    Applicant: SK hynix Inc.

    Inventor： Jin Woong KIM ,  Mi Seon LEE

    IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00

    Abstract: A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.

    SEMICONDUCTOR DIE HAVING A METAL PLATE LAYER
    7.
    发明申请
    SEMICONDUCTOR DIE HAVING A METAL PLATE LAYER 有权

    公开(公告)号：US20240395746A1

    公开(公告)日：2024-11-28

    申请号：US18497654

    申请日：2023-10-30

    Applicant: SK hynix Inc.

    Inventor： Jae Jun LEE ,  Sung Kyu KIM ,  Jong Yeon KIM ,  Ki Ill MOON ,  Mi Seon LEE

    IPC: H01L23/00 ,  H01L23/48 ,  H01L23/552

    Abstract: In an embodiment, a semiconductor die includes a substrate, an interlayer insulating layer under a front-side surface the substrate, a horizontal metal interconnection in the interlayer insulating layer, a front-side pad under a lower surface of the interlayer insulating layer, a front-side bump structure under a lower surface of the front-side pad, a through-electrode vertically passing through the substrate, a back-side insulating layer over the back-side surface of the substrate, a first back-side metal plate layer over the back-side insulating layer, a back-side passivation layer over the back-side insulating layer and covering the first back-side metal plate layer, and a back-side bump structure over the through-electrode and the back-side passivation layer.

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