公开(公告)号：US20180315796A1

公开(公告)日：2018-11-01

申请号：US15828014

申请日：2017-11-30

Applicant: SK hynix Inc.

Inventor： Jong Chul LEE ,  Jongho LEE

IPC: H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10

CPC classification number: H01L27/2463 ,  H01L23/528 ,  H01L27/224 ,  H01L27/2409 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1675

Abstract: A method of manufacturing a cross-point memory array device is disclosed. In the method, a substrate is provided. A plurality of first conductive line patterns are formed over the substrate. An insulating layer is formed over the first conductive line patterns. The insulating layer includes an insulative oxide. A plurality of switching film patterns are formed on the first conductive line patterns by selectively doping a plurality regions of the insulating layer. A plurality of memory structures are formed on the plurality of switching film patterns, respectively. A plurality of second conductive line patterns are formed on the plurality of memory structures.