公开(公告)号：US20160372595A1

公开(公告)日：2016-12-22

申请号：US15250217

申请日：2016-08-29

Applicant: SK hynix Inc.

Inventor： Jong Chul LEE ,  Min Yong LEE ,  Jin Ku LEE

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/36 ,  H01L21/84

CPC classification number: H01L29/7841 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/36 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The semiconductor substrate includes a semiconductor wafer, a silicon germanium (SiGe)-based impurity doping region formed on the semiconductor wafer, and a protection layer formed on the SiGe-based impurity doping region.

Abstract translation: 提供一种半导体衬底及其制造方法，以及使用其的半导体器件及其制造方法。 半导体衬底包括半导体晶片，形成在半导体晶片上的基于硅锗（SiGe）的杂质掺杂区域和形成在基于SiGe的杂质掺杂区域上的保护层。

公开(公告)号：US20140175537A1

公开(公告)日：2014-06-26

申请号：US13845693

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Min Yong LEE ,  Jin Ku LEE ,  Jong Chul LEE

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/26533 ,  H01L21/84

Abstract: The semiconductor apparatus includes a semiconductor substrate, an insulating layer formed in the semiconductor substrate to be spaced from a surface of the semiconductor substrate by a predetermined depth and formed to extend to a first direction to have a predetermined width, and an active region formed to be in contact with the semiconductor substrate below the insulating layer through a source post that is formed to vertically penetrate a predetermined portion of the insulating layer, and formed on the insulating layer and the source post to extend to the first direction to have a predetermined width.

Abstract translation: 半导体装置包括：半导体衬底;形成在半导体衬底中的绝缘层，以与半导体衬底的表面间隔预定深度并形成为延伸到具有预定宽度的第一方向;以及有源区形成为 通过形成为垂直穿过绝缘层的预定部分的源极与绝缘层下方的半导体衬底接触，并且形成在绝缘层和源极柱上以向第一方向延伸以具有预定宽度 。

公开(公告)号：US20190157346A1

公开(公告)日：2019-05-23

申请号：US16019346

申请日：2018-06-26

Applicant: SK hynix Inc.

Inventor： Jong Chul LEE

IPC: H01L27/24 ,  H01L45/00 ,  G06F3/06

CPC classification number: H01L27/2409 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16

Abstract: An electronic device having a semiconductor memory device is provided. The semiconductor memory device may include a lower interlayer insulating layer having a hole; an upper interlayer insulating layer disposed on the lower interlayer insulating layer; and a memory cell stack including a lower element and an upper element, the lower element being confined to the hole of the lower interlayer insulating layer, the upper element being surrounded by the upper interlayer insulating layer. The lower element may include a lower electrode and a selection element pattern disposed on the lower electrode. The upper element may include a memory pattern disposed on the selection element pattern and an upper electrode disposed on the memory pattern.

公开(公告)号：US20170338409A1

公开(公告)日：2017-11-23

申请号：US15402125

申请日：2017-01-09

Applicant: SK hynix Inc.

Inventor： Jong Chul LEE ,  Kyung Wan KIM

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/10 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/165

Abstract: A method of manufacturing a switching element includes forming a pillar-shaped structure over a substrate, performing a dopant injection process to form a first doping region in an insulation layer. The method further includes performing the dopant injection process to form a second doping region in a first electrode, to form a third doping region in a second electrode, or both. The pillar-shaped structure includes the first electrode, the insulation layer, and the second electrode that are disposed over a substrate. The first and second doping regions form a first interface therebetween, and the first and third doping regions form a second interface therebetween. The first doping region corresponds to a region in which a threshold switching operation region is performed.

公开(公告)号：US20130334670A1

公开(公告)日：2013-12-19

申请号：US13716011

申请日：2012-12-14

Applicant: SK HYNIX INC.

Inventor： Seung Beom BAEK ,  Su Jin CHAE ,  Min Yong LEE ,  Hye Jin SEO ,  Young Ho LEE ,  Jin Ku LEE ,  Jong Chul LEE

IPC: H01L29/868 ,  H01L21/02

CPC classification number: H01L29/868 ,  H01L21/02518 ,  H01L21/22 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66136

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a first type semiconductor layer doped with an N type ion, a second type semiconductor layer formed over the first type semiconductor layer, and a silicon germanium (SiGe) layer doped with a P type ion formed over the second type semiconductor layer.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括掺杂有N型离子的第一类型半导体层，在第一类型半导体层上形成的第二类型半导体层和在第二类型半导体层上形成的掺杂有P型离子的硅锗（SiGe）层 。

公开(公告)号：US20230413582A1

公开(公告)日：2023-12-21

申请号：US18058561

申请日：2022-11-23

Applicant: SK hynix Inc.

Inventor： Young-In BAE ,  Jong Chul LEE ,  Nam Joo KIM ,  Hong Seuk LEE

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/84 ,  H10N70/883 ,  H10N70/021

Abstract: A method for fabricating a semiconductor device, may include: providing a substrate; forming a first stacked structure over the substrate, the first stacked structure including a plurality of first lower lines extending in a first direction, a plurality of first upper lines disposed over the first lower lines and extending in a second direction intersecting the first direction, and a plurality of first memory cells respectively disposed at intersection regions between the first lower lines and the first upper lines; forming a first insulating layer filled between the first memory cells and between the first upper lines; forming a first space by recessing the first insulating layer to expose side surfaces of the first upper lines; and forming a second insulating layer having a higher etch resistance than the first insulating layer while filling the first space.

公开(公告)号：US20180315796A1

公开(公告)日：2018-11-01

申请号：US15828014

申请日：2017-11-30

Applicant: SK hynix Inc.

Inventor： Jong Chul LEE ,  Jongho LEE

IPC: H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10

CPC classification number: H01L27/2463 ,  H01L23/528 ,  H01L27/224 ,  H01L27/2409 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1675

Abstract: A method of manufacturing a cross-point memory array device is disclosed. In the method, a substrate is provided. A plurality of first conductive line patterns are formed over the substrate. An insulating layer is formed over the first conductive line patterns. The insulating layer includes an insulative oxide. A plurality of switching film patterns are formed on the first conductive line patterns by selectively doping a plurality regions of the insulating layer. A plurality of memory structures are formed on the plurality of switching film patterns, respectively. A plurality of second conductive line patterns are formed on the plurality of memory structures.

公开(公告)号：US20140322886A1

公开(公告)日：2014-10-30

申请号：US14323765

申请日：2014-07-03

Applicant: SK hynix Inc.

Inventor： Min Yong LEE ,  Young Ho LEE ,  Seung Beom BAEK ,  Jong Chul LEE

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2481 ,  H01L29/6609 ,  H01L29/861 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.

Abstract translation: 提供了一种电阻式存储器件及其制造方法。 电阻式存储器件包括形成在其上形成底部结构的半导体衬底上的可变电阻层，形成在可变电阻层上的下电极，形成在下电极上的开关单元和形成在开关单元上的上电极 。

公开(公告)号：US20140299918A1

公开(公告)日：2014-10-09

申请号：US13950625

申请日：2013-07-25

Applicant: SK hynix Inc.

Inventor： Jong Chul LEE ,  Min Yong LEE ,  Jin Ku LEE

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7841 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/36 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The semiconductor substrate includes a semiconductor wafer, a silicon germanium (SiGe)-based impurity doping region formed on the semiconductor wafer, and a protection layer formed on the SiGe-based impurity doping region.

Abstract translation: 提供一种半导体衬底及其制造方法，以及使用其的半导体器件及其制造方法。 半导体衬底包括半导体晶片，形成在半导体晶片上的基于硅锗（SiGe）的杂质掺杂区域和形成在基于SiGe的杂质掺杂区域上的保护层。

公开(公告)号：US20140054533A1

公开(公告)日：2014-02-27

申请号：US13715970

申请日：2012-12-14

Applicant: SK HYNIX INC.

Inventor： Jin Ku LEE ,  Min Yong LEE ,  Jong Chul LEE

IPC: H01L45/00

CPC classification number: H01L45/00 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/144

Abstract: A PCRAM device and a method of manufacturing the same are provided. The PCRAM device includes a semiconductor substrate, and a PN diode formed on the semiconductor substrate and including a layer interposed therein to suppress thermal diffusion of ions.

Abstract translation: 提供PCRAM装置及其制造方法。 PCRAM器件包括半导体衬底和形成在半导体衬底上的PN二极管，并且包括插入其中的层以抑制离子的热扩散。