公开(公告)号：US11656793B2

公开(公告)日：2023-05-23

申请号：US17501938

申请日：2021-10-14

Applicant: SK hynix Inc.

Inventor： Soo Jin Park ,  Ji Yeun Kang ,  Won Hyoung Lee

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0246 ,  G06F2212/7201

Abstract: A memory system includes a memory device including memory blocks, and a controller configured to in response to a program request or a read request for a selected memory block among the memory blocks being received from a host, store first data to which a first logical address is allocated in a cache group, generate a first entry for the first data stored in the cache group, and in response to second data to which the first logical address is allocated being stored in the cache group after the first data is stored in the cache group, generate a second entry for the second data.

公开(公告)号：US11543998B2

公开(公告)日：2023-01-03

申请号：US17036791

申请日：2020-09-29

Applicant: SK hynix Inc.

Inventor： Soo Jin Park

IPC: G06F3/06

Abstract: A storage device includes first and second memory devices, and a memory controller. The first memory devices correspond to a main data area. The second memory devices correspond to a reserved area. The memory controller is coupled to the first and second memory devices through first and second channels. A number of first memory devices coupled to the memory controller through the first channel is equal to a number of first memory devices coupled to the memory controller through the second channel, and a number of second memory devices coupled to the memory controller through the first channel is different from a number of second memory devices coupled to the memory controller through the second channel. The memory controller selects a memory device on which a write operation is to be performed, based on a memory state of the first and second memory devices.

公开(公告)号：US11531586B2

公开(公告)日：2022-12-20

申请号：US17330845

申请日：2021-05-26

Applicant: SK hynix Inc.

Inventor： Soo Jin Park ,  Won Hyoung Lee

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/07

Abstract: A memory system includes at least one semiconductor memory device including a plurality of memory blocks in which an original data stripe including a plurality of unit data and parity data is stored, and a controller configured to control an operation of the semiconductor memory device. The controller performs an error correction operation on one or more unit data received from the semiconductor memory device, and generates data for recovery based on remaining data except for first and second unit data among the plurality of unit data, in response to a first error correction failure for the first unit data among the plurality of unit data and a second error correction failure for the second unit data.