公开(公告)号：US20190065289A1

公开(公告)日：2019-02-28

申请号：US16113740

申请日：2018-08-27

Applicant: SK hynix memory solutions America Inc.

Inventor： Seong Won SHIN ,  Kyoungsun HONG

IPC: G06F9/54 ,  G06F9/50

Abstract: A data processing system includes a host device and a memory system including a controller and a memory device. The controller receives a command for the memory device from the host device, determines whether at least one slowdown event occurs due to an internal operation, and when it is determined that the slowdown event occurs, notifies the host device of occurrence of the slowdown event.

公开(公告)号：US20190250831A1

公开(公告)日：2019-08-15

申请号：US16276449

申请日：2019-02-14

Applicant: SK hynix memory solutions America Inc.

Inventor： Seong Won SHIN ,  Yi TONG ,  Seungwan JUNG

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1024 ,  G06F2212/7201

Abstract: A data processing system includes a host device and a memory system including a plurality of units. The host device includes a workload generation component and an analysis component. The workload generation component concurrently transmits, to the memory system, a plurality of commands for the plurality of memory units. The analysis component receives, from the memory system, command completion messages corresponding to the plurality of commands; measures latencies of the plurality of commands based on the receiving of the command completion messages; and analyze a parallelism scheme of the plurality of memory units based the measured latencies.