公开(公告)号：US20240064900A1

公开(公告)日：2024-02-22

申请号：US18260485

申请日：2021-12-23

Applicant: SONY GROUP CORPORATION

Inventor： KANAHIRO SHIROTA ,  KEIICHI HIRANO

IPC: H05K1/14 ,  H01R12/72 ,  H01R12/73 ,  H01R12/71

CPC classification number: H05K1/148 ,  H01R12/722 ,  H01R12/73 ,  H01R12/716 ,  H05K2201/10189 ,  H05K2201/042

Abstract: There is provided a multilayer electronic substrate that is reduced in size and thickness while reducing stress applied to a connector. The multilayer electronic substrate includes: a first substrate; a second substrate placed on the first substrate such that surfaces of the first and second substrates face each other; a first connector mounted on the surface of the first substrate and electrically connected to a first wire of the first substrate; a second connector mounted on the surface of the second substrate and electrically connected to a first wire of the second substrate, the second connector being directly connected to the first connector; and a wiring member having flexibility, the wiring member having one end electrically connected to a second wire of the first substrate and another end electrically connected to a second wire of the second substrate, to electrically connect the second wire of the first substrate and the second wire of the second substrate.