公开(公告)号：US11651227B2

公开(公告)日：2023-05-16

申请号：US16226286

申请日：2018-12-19

Applicant: SRI International

Inventor： Shalini Ghosh ,  Patrick Lincoln ,  Ashish Tiwari ,  Susmit Jha

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/084

CPC classification number: G06N3/084 ,  G06N3/0454

Abstract: In general, the disclosure describes techniques for facilitating trust in neural networks using a trusted neural network system. For example, described herein are multi-headed, trusted neural network systems that can be trained to satisfy one or more constraints as part of the training process, where such constraints may take the form of one or more logical rules and cause the objective function of at least one the heads of the trusted neural network system to steer, during machine learning model training, the overall objective function for the system toward an optimal solution that satisfies the constraints. The constraints may be non-temporal, temporal, or a combination of non-temporal and temporal. The constraints may be directly compiled to a neural network or otherwise used to train the machine learning model.

公开(公告)号：US11423247B2

公开(公告)日：2022-08-23

申请号：US16839982

申请日：2020-04-03

Applicant: SRI International

Inventor： Ashish Tiwari ,  Susmit Jha ,  Patrick Lincoln

IPC: H03M7/34 ,  H03M7/00 ,  G06K9/62 ,  G06F9/54 ,  H03M7/30 ,  H03M7/40

Abstract: Techniques are disclosed for identifying fixed bits of a bitstring format. One or more processors are configured to generate a first bitstring having respective first bit values that have a first satisfiability state and generate a second bitstring having respective second bit values that have a second satisfiability state. The one or more processors are configured to identify first potential free bits having respective first common values and generate a third bitstring having first potential free bits with the respective first common values and third remaining bits. The one or more processors are configured to identify second potential free bits having respective second common values and identify a fixed bit that is not included in the first potential free bits and is not included in the second potential free bits.