公开(公告)号：US09117812B2

公开(公告)日：2015-08-25

申请号：US14138382

申请日：2013-12-23

Applicant: STATS ChipPAC, Ltd.

Inventor： JaeHyun Lee ,  KiYoun Jang ,  KyungHoon Lee ,  TaeWoo Lee

IPC: H01L21/4763 ,  H01L23/12 ,  H01L23/498 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/4814 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电层。 绝缘层在第一基板的上方形成有第一导电层上的开口。 第二导电层形成在绝缘层的开口内。 去除第二导电层的一部分以暴露第二导电层在绝缘层的表面下方的水平表面和侧表面。 第二导电层具有非线性表面以延伸第二导电层的接触面积。 水平表面和侧表面可以是台阶表面或形成为环形。 在第二导电层上形成第三导电层。 在第二导电层的水平表面和侧表面上形成多个凸块。 将半导体管芯安装到基板上。

公开(公告)号：US20140103503A1

公开(公告)日：2014-04-17

申请号：US14138382

申请日：2013-12-23

Applicant: STATS ChipPAC, Ltd.

Inventor： JaeHyun Lee ,  KiYoun Jang ,  KyungHoon Lee ,  TaeWoo Lee

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49816 ,  H01L21/4814 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电层。 绝缘层在第一基板的上方形成有第一导电层上的开口。 第二导电层形成在绝缘层的开口内。 去除第二导电层的一部分以暴露第二导电层在绝缘层的表面下方的水平表面和侧表面。 第二导电层具有非线性表面以延伸第二导电层的接触面积。 水平表面和侧表面可以是台阶表面或形成为环形。 在第二导电层上形成第三导电层。 在第二导电层的水平表面和侧表面上形成多个凸块。 将半导体管芯安装到基板上。

公开(公告)号：US20130175701A1

公开(公告)日：2013-07-11

申请号：US13720516

申请日：2012-12-19

Applicant: STATS ChipPAC, Ltd.

Inventor： SeongWon Park ,  KiYoun Jang ,  KyungHoon Lee ,  JaeHyun Lee

IPC: H01L21/66 ,  H01L23/31

CPC classification number: H01L22/12 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/31 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers.

Abstract translation: 半导体器件包括半导体管芯。 在半导体管芯的有源表面上形成互连结构。 在半导体管芯和互连结构之上形成密封剂，其包括与互连结构相对的第一表面。 第一表面的周边部分包括设置在半导体管芯的占位面外的第一粗糙度。 第一表面的半导体管芯部分包括小于半导体管芯的覆盖区上的第一粗糙度的第二粗糙度。 密封剂的第一表面设置在模具内并且围绕半导体管芯接触模具的表面，该表面包括等于第一粗糙度的第三粗糙度和等于第二粗糙度的第四粗糙度。 第一粗糙度包括小于1.0微米的粗糙度。 第二粗糙度包括在1.2-1.8微米范围内的粗糙度。

公开(公告)号：US09679846B2

公开(公告)日：2017-06-13

申请号：US14572298

申请日：2014-12-16

Applicant: STATS ChipPAC, Ltd.

Inventor： JaeHyun Lee ,  SunJae Kim ,  JoongGi Kim

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L21/768 ,  H01L23/522 ,  H01L23/525 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L21/4867 ,  H01L21/563 ,  H01L21/565 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5221 ,  H01L23/5252 ,  H01L23/5256 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10175 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.

公开(公告)号：US09460972B2

公开(公告)日：2016-10-04

申请号：US13720516

申请日：2012-12-19

Applicant: STATS ChipPAC, Ltd.

Inventor： SeongWon Park ,  KiYoun Jang ,  KyungHoon Lee ,  JaeHyun Lee

IPC: H01L21/66 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L22/12 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/31 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers.

Abstract translation: 半导体器件包括半导体管芯。 在半导体管芯的有源表面上形成互连结构。 在半导体管芯和互连结构之上形成密封剂，其包括与互连结构相对的第一表面。 第一表面的周边部分包括设置在半导体管芯的占位面外的第一粗糙度。 第一表面的半导体管芯部分包括小于半导体管芯的覆盖区上的第一粗糙度的第二粗糙度。 密封剂的第一表面设置在模具内并且围绕半导体管芯接触模具的表面，该表面包括等于第一粗糙度的第三粗糙度和等于第二粗糙度的第四粗糙度。 第一粗糙度包括小于1.0微米的粗糙度。 第二粗糙度包括在1.2-1.8微米范围内的粗糙度。

公开(公告)号：US20150097295A1

公开(公告)日：2015-04-09

申请号：US14572298

申请日：2014-12-16

Applicant: STATS ChipPAC, Ltd.

Inventor： JaeHyun Lee ,  SunJae Kim ,  JoongGi Kim

IPC: H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L23/525 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/4867 ,  H01L21/563 ,  H01L21/565 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5221 ,  H01L23/5252 ,  H01L23/5256 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10175 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的多个凸点的半导体管芯。 具有第一和第二段的第一导电层形成在衬底的表面上，其中第一通气口分隔第一段和第二段的端部，第二通气口分隔第二段和第一段的一端。 第二导电层形成在衬底的表面上以电连接第一段和第二段。 第二导电层的厚度可以小于第一导电层的厚度，以形成第一通气孔和第二通气口。 将半导体管芯安装到衬底上，其中凸块与第一段和第二段对准。 凸块的回流材料的凸起材料被引导到第一通风口和第二排气口中。