公开(公告)号：US20250102574A1

公开(公告)日：2025-03-27

申请号：US18474511

申请日：2023-09-26

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Jain ,  Akshay Kumar Jain ,  Jeena Mary George

IPC: G01R31/319 ,  G01R31/317 ,  G01R31/3193

Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N-1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N-1 number of redundant flip-flops is observed through the functional path to determine faults.

公开(公告)号：US12265124B1

公开(公告)日：2025-04-01

申请号：US18474511

申请日：2023-09-26

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Jain ,  Akshay Kumar Jain ,  Jeena Mary George

IPC: G01R31/319 ,  G01R31/317 ,  G01R31/3193

Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N−1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N−1 number of redundant flip-flops is observed through the functional path to determine faults.