公开(公告)号：US11288143B2

公开(公告)日：2022-03-29

申请号：US17003808

申请日：2020-08-26

Applicant: STRATUS TECHNOLOGIES IRELAND LTD.

Inventor： Charles J. Horvath ,  Lei Cao

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/20 ,  G06F13/40

Abstract: In part, the disclosure relates to a real-time fault tolerant system. The system may include a first computing device, a second computing, and a hardware interconnect. The first computing device may include one or more memory devices, one or more processors, a first network interface operable to receive device data and transmit output data over a time-slot-based bus, wherein the output data is generated from processing device data, and a first real-time checkpoint engine. The second computing device may include similar components or the same components as the first computing device. The hardware interconnect is operable to permit data exchange between the first computing device and the second computing device. Checkpoints may be generated by checkpoint engines during lower-priority communication time slots allocated on the time slot-based bus to avoid interfering with any real-time communications to or from the first and second computing devices.