公开(公告)号：US11288143B2

公开(公告)日：2022-03-29

申请号：US17003808

申请日：2020-08-26

Applicant: STRATUS TECHNOLOGIES IRELAND LTD.

Inventor： Charles J. Horvath ,  Lei Cao

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/20 ,  G06F13/40

Abstract: In part, the disclosure relates to a real-time fault tolerant system. The system may include a first computing device, a second computing, and a hardware interconnect. The first computing device may include one or more memory devices, one or more processors, a first network interface operable to receive device data and transmit output data over a time-slot-based bus, wherein the output data is generated from processing device data, and a first real-time checkpoint engine. The second computing device may include similar components or the same components as the first computing device. The hardware interconnect is operable to permit data exchange between the first computing device and the second computing device. Checkpoints may be generated by checkpoint engines during lower-priority communication time slots allocated on the time slot-based bus to avoid interfering with any real-time communications to or from the first and second computing devices.

公开(公告)号：US20250130721A1

公开(公告)日：2025-04-24

申请号：US18399469

申请日：2023-12-28

Applicant: STRATUS TECHNOLOGIES IRELAND LTD.

Inventor： Michael Egan ,  Beverly Brown ,  Lei Cao ,  Steven Haid ,  Charles Horvath

IPC: G06F3/06

Abstract: In part, in one aspect, the disclosure relates to a first computer system including a first processor and first memory, a first IO storage subsystem including a first switch configured for one or more first storage devices, a first IO non-storage subsystem including a first which configured for one or more first non-storage devices, a second compute system including a second processor and second memory, a second storage IO subsystem including a second switch configured for one or more second storage devices, a second IO non-storage subsystem including a second switch configured for one or more second non-storage devices and a midplane including a power connector, a processor side and an IO side, wherein the processing side includes connectors in electrical communication with the computer systems, the IO side includes connectors in electrical communication with the storage and non-storage subsystems.

公开(公告)号：US20250130969A1

公开(公告)日：2025-04-24

申请号：US18399481

申请日：2023-12-28

Applicant: STRATUS TECHNOLOGIES IRELAND LTD.

Inventor： Lei Cao

IPC: G06F13/42

Abstract: In part, in one aspect, the disclosure relates to a method of enumerating a device relative to a computer system. The method may include sending, using a platform driver of an operating system (OS), a PCI memory range to self-enumeration (SE) firmware once it detects a new PCIe module; establishing a communication channel between the platform driver and SE firmware; detecting, using the platform driver, the new PCIe module via the PCI hotplug capability of the OS; and configuring a communication device, using the platform driver, on the PCIe module to establish a communication channel to the SE firmware. In some embodiments, the communication device is a synthetic device on the PCIe switch that allows low bandwidth bi-directional communication.