公开(公告)号：US20240176739A1

公开(公告)日：2024-05-30

申请号：US18072297

申请日：2022-11-30

Applicant: STRATUS TECHNOLOGIES IRELAND LTD.

Inventor： Andrew Alden ,  Chester Pawlowski ,  Christopher Cotton ,  John Chaves

IPC: G06F12/0815 ,  G06F12/0891

CPC classification number: G06F12/0815 ,  G06F12/0891 ,  G06F2212/1032

Abstract: In part, the disclosure relates to a fault tolerant system. The system may include one or more shared memory complexes, each memory complex comprising a group of M computer-readable memory storage devices; one or more cache coherent switches comprising two or more host ports and one or more downstream device ports, the cache coherent switch in electrical communication with the one or more shared memory storage device; a first management processor in electrical communication with the cache coherent switch; a first compute node comprising a first processor and a first cache, the first compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes; a second compute node comprising a second processor and a second cache, the second compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes.