中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

47 records (took 0.033 seconds)

    SEMICONDUCTOR DEVICE INCLUDING THROUGH VIA
    1.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING THROUGH VIA 有权

    公开(公告)号：US20250167107A1

    公开(公告)日：2025-05-22

    申请号：US18775049

    申请日：2024-07-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyungeun Choi ,  Taejin Park ,  Suklae Kim ,  Cheonbae Kim ,  Sungsoo Yim ,  Yoona Jang ,  Hyunyong Jeong

    IPC: H01L23/522 ,  G11C5/06 ,  H01L23/528 ,  H10B12/00

    Abstract: A semiconductor device is provided. The semiconductor device includes a first structure having a memory block region and an extension region; and a second structure having a peripheral circuit region. The first structure includes memory cells and a word line. The second structure includes a semiconductor body; a through-insulating pattern in the semiconductor body; and a peripheral transistor. The first and second structures include a word line signal path electrically connecting the word line to the peripheral transistor. The word line signal path includes a word line contact that is in contact with the word line in the extension region; a word line routing lower structure electrically connected to the word line contact and extending from the extension region into the memory block region; and a word line routing connection structure electrically connecting the word line routing lower structure to the word line routing peripheral structure.

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240349491A1

    公开(公告)日：2024-10-17

    申请号：US18534400

    申请日：2023-12-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myeong-Dong Lee ,  Jongmin Kim ,  Taejin Park ,  Seung-Bo Ko ,  Hui-Jung Kim

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/482 ,  H10B12/488

    Abstract: An example semiconductor memory device includes first and second active patterns, which are extended in a first direction and are disposed side by side in a second direction. Each of the first and second active patterns includes first and second edge portions, which are spaced apart from each other in the first direction. A pair of word lines are disposed to cross each of the first and second active patterns, a pair of bit lines are disposed on each of the first and second active patterns and are extended in a third direction, and a storage node contacts on the first edge portion of the first active pattern. When measured in the second direction, a first width of the storage node contact at a first level is larger than a second width at a second level. The first level is lower than the second level.

    Integrated circuit devices having buried word lines therein
    3.
    发明授权
    Integrated circuit devices having buried word lines therein 有权

    公开(公告)号：US11889681B2

    公开(公告)日：2024-01-30

    申请号：US17720664

    申请日：2022-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin Park ,  Taehoon Kim ,  Kyujin Kim ,  Chulkwon Park ,  Sunghee Han ,  Yoosang Hwang

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482

    Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

    Semiconductor devices and methods of forming semiconductor devices
    6.
    发明授权
    Semiconductor devices and methods of forming semiconductor devices 有权

    公开(公告)号：US10269808B2

    公开(公告)日：2019-04-23

    申请号：US15584342

    申请日：2017-05-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Taejin Park ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

    SEMICONDUCTOR DEVICE INCLUDING WORD LINE SIGNAL PATH
    7.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING WORD LINE SIGNAL PATH 有权

    公开(公告)号：US20250169066A1

    公开(公告)日：2025-05-22

    申请号：US18826334

    申请日：2024-09-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daesun Kim ,  Suklae Kim ,  Cheonbae Kim ,  Youngseok Park ,  Taejin Park ,  Hyunchul Yoon ,  Hyeonkyu Lee ,  Sungsoo Yim ,  Hyungeun Choi

    IPC: H10B12/00 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: Provided is a semiconductor device. The semiconductor device includes: a first connection region, a first memory block region, and a second connection region sequentially arranged; a first peripheral circuit region vertically overlapping with the first memory block region; first memory cells in the first memory block region; a first word line extending into the first and second connection regions by crossing the first memory block region, and electrically connected to the first memory cells; a first sub-word line driver in the first peripheral circuit region; and a first word line signal path electrically connecting the first word line and the first sub-word line driver. The first word line signal path includes at least one first routing contact coupled to the first word line in the first connection region, and at least one second routing contact coupled to the first word line in the second connection region.

    SEMICONDUCTOR DEVICES
    8.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250151260A1

    公开(公告)日：2025-05-08

    申请号：US18739698

    申请日：2024-06-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehyuk Kim ,  Taejin Park ,  Hyeran Lee ,  Sungsoo Yim

    IPC: H10B12/00 ,  H01L29/78

    Abstract: A semiconductor device includes bit line structures spaced apart from each other in a first direction, and each of the bit line structures extends in a second direction; channels on the bit line structures, wherein the channels are electrically connected to the bit line structures and spaced apart from each other in the first direction; a gate insulation pattern structure on sidewalls of each of the channels; a gate electrode structure including: a first gate electrode on a first sidewall of the gate insulation pattern structure; and a second gate electrode on a second sidewall of the gate insulation pattern structure, wherein the second sidewall faces the first sidewall in the second direction, wherein the second gate electrode is on a third sidewall in the first direction of an end portion of the gate insulation pattern structure, and wherein the second gate electrode contacts the first gate electrode.

Patent Agency Ranking