公开(公告)号：US20230389287A1

公开(公告)日：2023-11-30

申请号：US18144885

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeongjoo Ku ,  Keunnam Kim ,  Kiseok Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor device includes: a substrate including a cell array area, a periphery circuit area, and an interface area; bit lines arranged in the cell array area and extending in a first horizontal direction; a mold insulating layer arranged on the bit lines and including openings extending in a second horizontal direction; channel layers respectively arranged on the bit lines in each of the openings; word lines respectively arranged on the channel layers and extending in the second horizontal direction from the cell array area to the interface area, the word lines including a first word line on a first sidewall of each opening of the mold insulating layer and a second word line on a second sidewall of the opening; and a trimming insulating block arranged in the interface area and connected to an end of the first word line and an end of the second word line.

公开(公告)号：US11152368B2

公开(公告)日：2021-10-19

申请号：US16908833

申请日：2020-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonyoung Choi ,  Byunghyun Lee ,  Seungjin Kim ,  Byeongjoo Ku ,  Sangjae Park ,  Hangeol Lee

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a substrate, a storage node electrode disposed on the substrate, a dielectric layer at least partially covering the storage node electrode, and a plate electrode dispose on the dielectric layer. The storage node electrode has a pillar shape, and includes a seam disposed therein. The storage node electrode includes a concave side surface disposed at a higher level than the seam.

公开(公告)号：US20230354582A1

公开(公告)日：2023-11-02

申请号：US18062825

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Byeongjoo Ku ,  Keunnam Kim ,  Wonsok Lee ,  Moonyoung Jeong ,  Min Hee Cho

IPC: H01L29/94

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor device may include a bit line extending in a first direction, a semiconductor pattern on the bit line, the semiconductor pattern including first and second vertical portions, which are opposite to each other in the first direction, and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion to be adjacent to the first and second vertical portions, respectively, and a gate insulating pattern between the first vertical portion and the first word line and between the second vertical portion and the second word line. A bottom surface of the horizontal portion may be located at a height that is lower than or equal to the uppermost surface of the bit line.

公开(公告)号：US20210151439A1

公开(公告)日：2021-05-20

申请号：US16908833

申请日：2020-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOONYOUNG CHOI ,  Byunghyun Lee ,  Seungjin Kim ,  Byeongjoo Ku ,  Sangjae Park ,  Hangeol Lee

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes a substrate, a storage node electrode disposed on the substrate, a dielectric layer at least partially covering the storage node electrode, and a plate electrode dispose on the dielectric layer. The storage node electrode has a pillar shape, and includes a seam disposed therein. The storage node electrode includes a concave side surface disposed at a higher level than the seam.

公开(公告)号：US20230380173A1

公开(公告)日：2023-11-23

申请号：US18101606

申请日：2023-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeongjoo Ku ,  Keunnam Kim ,  Kiseok Lee

IPC: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H01L23/528 ,  G11C16/08 ,  G11C16/26

CPC classification number: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H01L23/5283 ,  G11C16/08 ,  G11C16/26

Abstract: A semiconductor memory device includes a semiconductor substrate, a peripheral circuit structure disposed on the semiconductor substrate, and a cell array structure located on the peripheral circuit structure and including a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells of the cell array structure includes a bit line extending in a first horizontal direction, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a first word line extending in a second horizontal direction crossing the first horizontal direction on the channel pattern, a first gate insulating pattern located between the channel pattern and the first word line, a landing pad connected to the vertical channel portion of the channel pattern, and a data storage pattern disposed on the landing pad.

公开(公告)号：US11462610B2

公开(公告)日：2022-10-04

申请号：US16947090

申请日：2020-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung Choi ,  Byunghyun Lee ,  Byeongjoo Ku ,  Seungjin Kim ,  Sangjae Park ,  Jinwoo Bae ,  Hangeol Lee ,  Bowo Choi ,  Hyunsil Hong

IPC: H01L27/108 ,  H01L49/02

Abstract: Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.