公开(公告)号：US20240402941A1

公开(公告)日：2024-12-05

申请号：US18644558

申请日：2024-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehun Jang ,  Sumin Kim ,  Jiwon Seo ,  Mankeun Seo ,  Hongrak Son ,  Dongmin Shin

IPC: G06F3/06

Abstract: A memory device includes first and second memory cell arrays each including a plurality of memory cells, a page buffer circuit configured to read first soft decision data including a plurality of sub-segments from the first memory cell array, and a compression circuit configured to perform a first compression operation of generating a first compression segment including a number of position values less than or equal to a first reference number, on each of a plurality of partial segments included in one of the plurality of sub-segments and sequentially perform a plurality of compression operations, which is subsequent to the first compression operation, of generating a next compression segment including a number of position values, which are less than or equal to a reference number corresponding to each compression operation, of position values included in two or more previous compression segments in each compression operation.

公开(公告)号：US12045132B2

公开(公告)日：2024-07-23

申请号：US18156893

申请日：2023-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongmin Shin ,  Jinyoung Kim ,  Sehwan Park ,  Youngdeok Seo

IPC: G06F11/10 ,  H03M13/45

CPC classification number: G06F11/1068 ,  H03M13/45

Abstract: A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.

公开(公告)号：US11775203B2

公开(公告)日：2023-10-03

申请号：US17376437

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeok Seo ,  Jinyoung Kim ,  Sehwan Park ,  Dongmin Shin ,  Woohyun Kang ,  Shinho Oh

IPC: G06F3/00 ,  G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0655 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/0679 ,  G06N3/08

Abstract: A method of operating a nonvolatile memory device is provided. The method includes: dividing a memory block of a plurality of memory blocks provided in the nonvolatile memory device into a plurality of retention groups; generating time-difference information including a plurality of erase program interval (EPI) values corresponding to the plurality of retention groups; generating offset information including a plurality of offset values corresponding to differences between a plurality of default read voltages and a plurality of corrected read voltages; generating compensated read voltages corresponding to a read address based on the offset information and the time-difference information; and performing a read operation to read data from the nonvolatile memory device based on the read address and the compensated read voltages.

公开(公告)号：US20220139475A1

公开(公告)日：2022-05-05

申请号：US17328487

申请日：2021-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeok SEO ,  Jinyoung Kim ,  Sehwan Park ,  Dongmin Shin

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G06K9/62 ,  G06N20/10

Abstract: A non-volatile memory device includes a memory cell array including memory cells, a page buffer circuit including page buffers respectively connected to bit lines, a buffer memory, and a control logic configured to control a read operation on the memory cells. In the read operation, the control logic obtains valley search detection information including read target block information and word line information by performing a valley search sensing operation on a distribution of threshold voltages of the memory cells, obtains a plurality of read levels using a read information model by inputting the valley search detection information into the read information model, and performs a main sensing operation for the read operation.

公开(公告)号：US12067287B2

公开(公告)日：2024-08-20

申请号：US17685024

申请日：2022-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanwoo Noh ,  Hyeonjong Song ,  Wijik Lee ,  Hongrak Son ,  Dongmin Shin ,  Seonghyeog Choi

IPC: G06F3/06 ,  G11C16/04

CPC classification number: G06F3/0658 ,  G06F3/0614 ,  G06F3/0679 ,  G11C16/0483

Abstract: Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.

公开(公告)号：US11562804B2

公开(公告)日：2023-01-24

申请号：US17469422

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Youngdeok Seo ,  Dongmin Shin ,  Joonsuc Jang ,  Sungmin Joe

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C16/10 ,  G11C29/12 ,  G11C16/26

Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

公开(公告)号：US20220182073A1

公开(公告)日：2022-06-09

申请号：US17478002

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KANGSEOK LEE ,  Geunyeong Yu ,  Heeyoul Kwak ,  Hongrak Son ,  Dongmin Shin ,  Wijik Lee ,  Bohwan Jun ,  Youngjun Hwang

IPC: H03M13/09 ,  H03M13/11 ,  H03M13/15 ,  H03M13/29

Abstract: A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.

公开(公告)号：US20240429943A1

公开(公告)日：2024-12-26

申请号：US18584838

申请日：2024-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kijun Jeon ,  Kyoungbin Park ,  Minki Song ,  Dongmin Shin ,  Daeyeol Yang ,  Bohwan Jun ,  Youngjun Hwang

IPC: H03M13/11 ,  H03M13/00

Abstract: An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.

公开(公告)号：US20240427520A1

公开(公告)日：2024-12-26

申请号：US18737403

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonyoung Kang ,  Dongmin Shin

IPC: G06F3/06

Abstract: An example memory system includes a memory device and a memory controller. The memory device is configured to read, from a memory cell array, hard decision data based on a hard read voltage and first soft decision data based on first soft read voltages obtained based on the hard read voltage and a first voltage offset, generate a first compressed sub-segment based on encoding a position of a bit having a first value into a position value for each of first soft decision sub-segments in the first soft decision data, and output first compressed data including first compressed sub-segments. The memory controller is configured to receive the first compressed data, count the number of position values in each of the first compressed sub-segments, and provide, to the memory device based on the counted number, a command to request a change of a voltage offset and a recompression operation.

公开(公告)号：US20240356565A1

公开(公告)日：2024-10-24

申请号：US18643302

申请日：2024-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangseok Lee ,  Bohwan Jun ,  Youngjun Hwang ,  Dongmin Shin

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/37

CPC classification number: H03M13/1174 ,  H03M13/1575 ,  H03M13/3746

Abstract: An example operating method of an error correction code (ECC) circuit includes receiving a codeword from a memory device, calculating a syndrome vector based on the codeword and a parity-check matrix indicating whether messages are exchanged between check nodes and variable nodes, performing, when the syndrome vector is not a zero vector, sequential decoding on a plurality of columns of the parity-check matrix by decoding a first column in a first operation mode, the first column having a first variable node degree, decoding a second column in a second operation mode, the second column having a second variable node degree, and decoding a third column in a third operation mode, the third column having a third variable node degree, and calculating the syndrome vector whenever the sequential decoding of the plurality of columns is completed and iteratively performing the sequential decoding until the syndrome vector is the zero vector.