Chip on film package with trench to reduce slippage and display device including the same

    公开(公告)号:US12148337B2

    公开(公告)日:2024-11-19

    申请号:US17679587

    申请日:2022-02-24

    Abstract: A chip on film package is provided. The chip on film package includes a film substrate with a base film, a conductive pad extending in a first direction on the base film, and a conductive line pattern extending from the conductive pad; a semiconductor chip provided on the film substrate; and a bump structure provided between the semiconductor chip and the conductive pad. A first peripheral wall and a second peripheral wall of the bump structure extend in the first direction and define a trench, a portion of the conductive pad is provided in the trench, and the conductive pad is spaced apart from at least one of the first peripheral wall and the second peripheral wall.

    CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME

    公开(公告)号:US20220139799A1

    公开(公告)日:2022-05-05

    申请号:US17508483

    申请日:2021-10-22

    Abstract: A chip-on-film package includes a base film including an upper surface and a lower surface that opposite from each other, a semiconductor chip mounted on the upper surface of the base film, a heat emission layer disposed on the lower surface of the base film to at least partially overlap the semiconductor chip in a thickness direction, an insulating layer disposed on a lower surface of the heat emission layer, and a protective layer surrounding side and lower surfaces of the insulating layer. Accordingly, thermal fatigue of the chip-on-film package may be reduced, and reliability may be increased.

    Chip-on-film package and display apparatus including the same

    公开(公告)号:US12230576B2

    公开(公告)日:2025-02-18

    申请号:US17579635

    申请日:2022-01-20

    Abstract: A chip on film (COF) package includes a base film having an upper surface and a lower surface opposite to each other, a bridge film having an edge that overlaps the base film, and an upper surface and a lower surface opposite to each other, a display driver integrated circuit (IC) mounted on the upper surface of the base film, and a heat dissipation member arranged in correspondence with the display driver IC on the lower surface of the base film. The upper surface of the base film and the lower surface of the bridge film adhere to each other in their respective long axis directions, and a long axis length of the bridge film is greater than a long axis length of the base film.

    Electronic device for displaying plurality of application execution screens, and method related thereto

    公开(公告)号:US12190132B2

    公开(公告)日:2025-01-07

    申请号:US18116654

    申请日:2023-03-02

    Abstract: An electronic device includes: a foldable display; a processor operationally coupled with the display; and a memory operationally coupled with the processor, wherein the memory stores instructions that, when executed, cause the processor to: detect a screen layout state of the foldable display based on at least one of a folding angle of the foldable display, a rotation angle of the foldable display, a mounting state of the electronic device, or a gripped state of the electronic device; determine a plurality of applications for execution, based on the detected screen layout state; determine a plurality of regions of the foldable display on which the plurality of applications are to be displayed, based on the detected screen layout state; and display execution screens of the plurality of applications on the plurality of regions.

    CHIP-ON-FILM PACKAGE AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20240321902A1

    公开(公告)日:2024-09-26

    申请号:US18612828

    申请日:2024-03-21

    CPC classification number: H01L27/124

    Abstract: A chip of film package comprises a film substrate having a chip mounting region, an inner lead bonding region arranged within the chip mounting region, and an outer lead bonding region spaced apart from the inner lead bonding region in a first direction, and providing upper and lower surfaces opposite to each other, a first upper wiring pattern arranged on the upper surface of the film substrate and extending in the first direction from the inner lead bonding region to the outer lead bonding region, a second upper wiring pattern spaced apart from the first upper wiring pattern in the first direction, an upper solder resist layer covering an upper surface of the first upper wiring pattern; and a lower solder resist layer covering an upper surface of the lower wiring pattern.

    WAFER CLEANING APPARATUS
    6.
    发明申请

    公开(公告)号:US20250040693A1

    公开(公告)日:2025-02-06

    申请号:US18438750

    申请日:2024-02-12

    Abstract: A wafer cleaning apparatus includes a wafer roller rotating a wafer around a first direction parallel to a normal direction of a first surface of the wafer, a first brush facing the first surface of the wafer, a second brush facing a second surface of the wafer opposite to the first surface, a first cleaning tank disposed apart from the first brush and movable to accommodate at least a portion of the first brush, and a second cleaning tank disposed apart from the second brush and movable to accommodate at least a portion of the second brush. The first and second cleaning tanks include a first solution injection member connected to a first solution supply pipe and a second solution injection member connected to a second solution supply pipe, respectively. Each of the first and second solution injection members includes a bubble generating filter having a plurality of through-holes.

    CONDITIONING APPARATUS
    7.
    发明公开

    公开(公告)号:US20240269798A1

    公开(公告)日:2024-08-15

    申请号:US18402471

    申请日:2024-01-02

    CPC classification number: B24B37/20

    Abstract: A conditioning apparatus includes an arm configured to be rotated by an actuator, a gimbaling part disposed at one end of the arm and disposed such that a lower end thereof protrudes outwardly of the arm and an abrasive disc is installed thereon, a frame unit connected to the gimbaling part, a rotation driving unit connected to the gimbaling part and configured to transfer driving force for rotating the abrasive disc, a load applying unit connected to the frame unit and configured to elevate the frame unit, and a universal joint connecting the gimbaling part to the rotation driving unit, wherein the universal joint separates a center of gravity of the rotation driving unit from a center of gravity of the gimbaling part.

    NON-VOLATILE MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:US20240224523A1

    公开(公告)日:2024-07-04

    申请号:US18493853

    申请日:2023-10-25

    CPC classification number: H10B43/27 H10B41/27 H10B41/41 H10B43/40

    Abstract: A non-volatile memory device includes a substrate, a mold structure including a plurality of gate electrodes and a plurality of mold insulating layers, wherein the plurality of gate electrodes are stacked in a step shape, a channel structure that extends through the mold structure, and a cell contact that extends through the mold structure, the cell contact is connected to a first gate electrode, and the cell contact is not electrically connected to a second gate electrode among the plurality of gate electrodes, wherein the first gate electrode includes: an extension portion; a pad portion having a vertical thickness greater than a vertical thickness of the extension portion; and a connection portion that electrically connects the pad portion to the cell contact, the connection portion has a vertical thickness less than a vertical thickness of the pad portion, and one or more first insulating rings on the connection portion.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:US20240074195A1

    公开(公告)日:2024-02-29

    申请号:US18308262

    申请日:2023-04-27

    CPC classification number: H10B43/27 H10B43/40

    Abstract: A semiconductor device includes a conductive pattern, an insulating pattern, a channel film extending in a vertical direction inside a channel hole, a charge trap pattern between the conductive pattern and the channel film inside the channel hole, a tunneling dielectric film between the charge trap pattern and the channel film, and a blocking dielectric film extending between the conductive pattern and the charge trap pattern and between the insulating pattern and the tunneling dielectric film. The insulating pattern includes a first insulating pattern overlapping the conductive pattern in the vertical direction and a second insulating pattern protruding in the lateral direction from the first insulating pattern into the channel hole and toward the channel film. The first insulating pattern has a first dielectric constant, and the second insulating pattern has a second dielectric constant that is lower than the first dielectric constant.

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