公开(公告)号：US20240321902A1

公开(公告)日：2024-09-26

申请号：US18612828

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narae Shin ,  Jeongkyu Ha ,  Woonbae Kim ,  Yechung Chung ,  Jaemin Jung

IPC: H01L27/12

CPC classification number: H01L27/124

Abstract: A chip of film package comprises a film substrate having a chip mounting region, an inner lead bonding region arranged within the chip mounting region, and an outer lead bonding region spaced apart from the inner lead bonding region in a first direction, and providing upper and lower surfaces opposite to each other, a first upper wiring pattern arranged on the upper surface of the film substrate and extending in the first direction from the inner lead bonding region to the outer lead bonding region, a second upper wiring pattern spaced apart from the first upper wiring pattern in the first direction, an upper solder resist layer covering an upper surface of the first upper wiring pattern; and a lower solder resist layer covering an upper surface of the lower wiring pattern.

公开(公告)号：US20250087562A1

公开(公告)日：2025-03-13

申请号：US18816740

申请日：2024-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Narae Shin ,  Jeongkyu Ha ,  Woonbae Kim ,  Yechung Chung

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A chip on film package includes a base film having a first surface and a second surface which are opposite to each other, at least one first conductive line disposed on the first surface and extending in a first direction, at least one second conductive line disposed on the second surface and extending in the first direction, a semiconductor chip disposed on the first surface and connected to the at least one first conductive line through a bump structure, a protective layer covering a part of the first surface and a part of the second surface, and a display panel disposed on the first surface and connected to the at least one first conductive line, wherein the at least one second conductive line is not disposed on the second surface between the semiconductor chip and the display panel.

公开(公告)号：US20230420349A1

公开(公告)日：2023-12-28

申请号：US18125409

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narae Shin ,  Seongho Shin ,  Seonghwan Jeon

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/4985 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16227 ,  H01L23/3107

Abstract: A semiconductor package includes a base film, a first conductive structure disposed on a first surface of the base film, a second conductive structure disposed on a second surface of the base film, a via passing through the base film and connecting the first conductive structure to the second conductive structure, a semiconductor chip on the first surface and electrically connected to the first conductive structure, a first insulating layer covering the first conductive structure and including a first opening exposing a first conductive pattern of the first conductive structure, a first conductive layer disposed on the first insulating layer, covering the first insulating layer and the semiconductor chip, and contacting a region of the first conductive pattern exposed by the first opening, and a second conductive layer disposed on the second surface, covering the second conductive structure, and contacting at least a portion of the second conductive structure.

公开(公告)号：US09313889B2

公开(公告)日：2016-04-12

申请号：US14262658

申请日：2014-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungsuk Yang ,  Jeong-Kyu Ha ,  PaLan Lee ,  Narae Shin ,  Soyoung Lim ,  Jae-Min Jung ,  KyongSoon Cho

IPC: H05B33/00 ,  H05K1/02 ,  H05K5/00 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18

CPC classification number: H05K1/118 ,  H05K1/147 ,  H05K1/189 ,  H05K2201/0949 ,  H05K2201/10128

Abstract: Provided is a display apparatus. The display apparatus includes a display panel, a flexible circuit film having a rear surface connected to the display panel, and a front surface opposite to the rear surface, the front surface having a chip mounted thereon, and a first lead bonding portion electrically connecting the chip to the display panel. The first lead bonding portion includes a first portion connected to the chip and overlying a portion of the flexible circuit film, a second portion passing through the flexible circuit film, and a third portion disposed between the flexible circuit film and the display panel on the rear surface of the flexible circuit film, where the third portion overlaps the first portion.

Abstract translation: 提供了一种显示装置。 显示装置包括显示面板，具有连接到显示面板的后表面的柔性电路薄膜和与背面相对的前表面，前表面具有安装在其上的芯片，以及第一引线接合部分， 芯片到显示面板。 第一引线接合部分包括连接到芯片并覆盖柔性电路膜的一部分的第一部分，穿过柔性电路膜的第二部分和设置在柔性电路膜和后面的显示面板之间的第三部分 柔性电路膜的表面，其中第三部分与第一部分重叠。

公开(公告)号：US20150269911A1

公开(公告)日：2015-09-24

申请号：US14581356

申请日：2014-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungpil CHOI ,  Hyungwoo Yu ,  Narae Shin ,  Kijoon Kim ,  Yong-Hun Kim ,  SooJin Park ,  Myoungsik Suh ,  Jae-Bum Lee ,  EunJong Jang

IPC: G09G5/18 ,  H01L23/50 ,  H01L23/522 ,  H01L23/00 ,  H01L27/12 ,  H01L23/528

CPC classification number: H01L23/50 ,  G09G5/005 ,  G09G2300/0404 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2340/0435 ,  H01L23/49822 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/08 ,  H01L2224/04105 ,  H01L2224/06153 ,  H01L2224/08237

Abstract: Provided is a chip on film package including an integrated circuit chip and a film. The integrated circuit chip includes one or more first output pads along a first longer side, and one or more second output pads along a second longer side which faces the first longer side. The film includes a lower film, a plurality of film conducting wires on one face of the lower film, and an upper film on the plurality of film conducting wires. Each of the plurality of film conducting wires may be spaced apart from an adjacent film conducting wire. The first output pads and the second output pads are respectively connected to the plurality of film conducting wires electrically. The plurality of film conducting wires is a single layer between the upper film and the lower film.

Abstract translation: 提供了包括集成电路芯片和薄膜的薄膜封装芯片。 集成电路芯片包括沿着第一长边的一个或多个第一输出焊盘，以及沿着第二长边的面向第一长边的一个或多个第二输出焊盘。 该膜包括下膜，在下膜的一个面上的多个膜导电丝和多个膜导电线上的上膜。 多个膜导电线中的每一个可以与相邻的膜导电线分开。 第一输出焊盘和第二输出焊盘分别电连接到多个膜导电线。 多个膜导电线是上膜和下膜之间的单层。