MEMORY DEVICE FOR IMPLEMENTING MULTI-LEVEL MEMORY AND METHOD OF IMPLEMENTING MULTI-LEVEL MEMORY BY USING THE MEMORY DEVICE

    公开(公告)号:US20250149084A1

    公开(公告)日:2025-05-08

    申请号:US18785752

    申请日:2024-07-26

    Abstract: Provided are a memory device for implementing a multi-level memory and a method of implementing a multi-level memory by using the memory device. The memory device includes first and second electrodes apart from each other, a self-selecting memory layer between the first and second electrodes having an ovonic threshold switching characteristic, including a chalcogenide-based material, and configured to have a threshold voltage varying depending on a polarity of and strength of a voltage applied thereto, and a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto. The memory device is configured to implement multi-level resistance states by changing at least one of a pulse polarity, a number of pulses, pulse height, and a pulse width of a voltage applied between the first and second electrodes.

    SEMICONDUCTOR APPARATUS
    10.
    发明公开

    公开(公告)号:US20230354725A1

    公开(公告)日:2023-11-02

    申请号:US18349433

    申请日:2023-07-10

    Abstract: A semiconductor apparatus may include a plurality of semiconductor unit devices. Each of the semiconductor unit devices may be arranged between a first insulating layer and a second insulating layer that are apart from each other in a direction normal to a substrate. Each of the semiconductor unit devices may include a selection device layer and a phase change material layer that extend side by side in a direction parallel to the substrate. The phase change material layer may have a superlattice-like structure. The phase change material layer may be arranged along a recess portion that is formed by the first insulating layer, the second insulating layer, and the selection device layer.

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