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    Method of forming an integrated circuit devices having buried word lines
    1.
    发明授权
    Method of forming an integrated circuit devices having buried word lines 有权

    公开(公告)号：US12207456B2

    公开(公告)日：2025-01-21

    申请号：US18525187

    申请日：2023-11-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin Park ,  Taehoon Kim ,  Kyujin Kim ,  Chulkwon Park ,  Sunghee Han ,  Yoosang Hwang

    IPC: H10B12/00

    Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

    INTEGRATED CIRCUIT DEVICES HAVING BURIED WORD LINES THEREIN AND METHODS OF FORMING THE SAME
    2.
    发明申请
    INTEGRATED CIRCUIT DEVICES HAVING BURIED WORD LINES THEREIN AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20250113482A1

    公开(公告)日：2025-04-03

    申请号：US18980204

    申请日：2024-12-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin Park ,  Taehoon Kim ,  Kyujin Kim ,  Chulkwon Park ,  Sunghee Han ,  Yoosang Hwang

    IPC: H10B12/00

    Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer.

    Semiconductor memory devices
    3.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11889682B2

    公开(公告)日：2024-01-30

    申请号：US17373539

    申请日：2021-07-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin Park ,  Kyujin Kim ,  Chulkwon Park ,  Sunghee Han

    IPC: H10B12/00

    CPC classification number: H10B12/50 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

    Abstract: A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction.

    INTEGRATED CIRCUIT DEVICE
    4.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20230402518A1

    公开(公告)日：2023-12-14

    申请号：US18202085

    申请日：2023-05-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin Park ,  Kyujin Kim ,  Bongsoo Kim ,  Huijung Kim ,  Pyung Moon ,  Chulkwon Park ,  Gyunghyun Yoon ,  Heejae Chae

    IPC: H01L29/423 ,  H10B12/00 ,  H01L29/49

    CPC classification number: H01L29/4236 ,  H10B12/315 ,  H01L29/4916

    Abstract: An integrated circuit (IC) device includes a gate trench formed inside a substrate, the gate trench including a bottom portion and a sidewall portion, a gate electrode structure disposed apart from the bottom portion and the sidewall portion of the gate trench, the gate electrode structure including a gate electrode including a first sub-gate electrode formed in a lower portion of the gate trench and a second sub-gate electrode formed on the first sub-gate electrode and a gate capping layer formed on the second sub-gate electrode, and a gate insulating layer formed between the gate trench and the gate electrode structure, the gate insulating layer including a base insulating layer formed between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure and a reinforcing insulating layer formed on a sidewall portion of the second sub-gate electrode.

    Integrated circuit devices having buried word lines therein
    6.
    发明授权
    Integrated circuit devices having buried word lines therein 有权

    公开(公告)号：US11889681B2

    公开(公告)日：2024-01-30

    申请号：US17720664

    申请日：2022-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin Park ,  Taehoon Kim ,  Kyujin Kim ,  Chulkwon Park ,  Sunghee Han ,  Yoosang Hwang

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482

    Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

    INTEGRATED CIRCUIT DEVICES HAVING BURIED WORD LINES THEREIN AND METHODS OF FORMING THE SAME
    7.
    发明申请
    INTEGRATED CIRCUIT DEVICES HAVING BURIED WORD LINES THEREIN AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20220344344A1

    公开(公告)日：2022-10-27

    申请号：US17720664

    申请日：2022-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin Park ,  Taehoon Kim ,  Kyujin Kim ,  Chulkwon Park ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

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