公开(公告)号：US20220223713A1

公开(公告)日：2022-07-14

申请号：US17702856

申请日：2022-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naoto Umezawa ,  Satoru Yamada ,  Junsoo Kim ,  Honglae Park ,  Chunhyung Chung

IPC: H01L29/51 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.

公开(公告)号：US12181799B2

公开(公告)日：2024-12-31

申请号：US16947515

申请日：2020-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Thanh Cuong Nguyen ,  Daekeon Kim ,  Tsunehiro Nishi ,  Naoto Umezawa ,  Hyunwoo Kim

IPC: G03F7/004 ,  C07C25/13 ,  G03F7/038 ,  G03F7/039 ,  H01L21/027

Abstract: Disclosed are resist compositions and semiconductor device fabrication methods wing the same. The resist composition comprises a hypervalent iodine compound of Chemical Formula 1 below. Wherein R1 to R7 are as defined herein.

公开(公告)号：US11329137B2

公开(公告)日：2022-05-10

申请号：US16927463

申请日：2020-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naoto Umezawa ,  Satoru Yamada ,  Junsoo Kim ,  Honglae Park ,  Chunhyung Chung

IPC: H01L29/51 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.

公开(公告)号：US20220207393A1

公开(公告)日：2022-06-30

申请号：US17468819

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naoto Umezawa ,  Changwook Jeong ,  Jisu Ryu ,  Kyu Hyun Lee ,  Jinyoung Lim ,  Wonik Jang ,  In Huh

IPC: G06N5/04 ,  G06N5/02

Abstract: Disclosed are methods of predicting semiconductor material properties and methods of testing semiconductor devices using the same. The prediction method comprises preparing a machine learning model that is trained with a training system and using the machine learning model to predict material properties of a target system. The machine learning model is represented as a function of material properties with respect to a descriptor. The descriptor is calculated from unrelaxed charge density (UCD) that is represented by summation of atomic charge density (ACD) of single atoms.

公开(公告)号：US20210134975A1

公开(公告)日：2021-05-06

申请号：US16927463

申请日：2020-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naoto Umezawa ,  Satoru Yamada ,  Junsoo Kim ,  Honglae Park ,  Chunhyung Chung

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L27/108

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.