公开(公告)号：US20220336326A1

公开(公告)日：2022-10-20

申请号：US17517291

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SHAOFENG DING ,  SUNGWOOK MOON ,  JEONGHOON AHN ,  YUNKI CHOI

IPC: H01L23/48 ,  H01L23/522 ,  H01L25/065

Abstract: A semiconductor chip may include; a device layer including transistors on a substrate, a wiring layer on the device layer, a first through via passing through the device layer and the substrate, and a second through via passing through the wiring layer, the device layer and the substrate, wherein a first height of the first through via is less than a second height of the second through via.

公开(公告)号：US20220384563A1

公开(公告)日：2022-12-01

申请号：US17559176

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIHYUNG KIM ,  JEONGHOON AHN ,  JAEHEE OH ,  SHAOFENG DING ,  WONJI PARK ,  JEGWAN HWANG

IPC: H01L49/02 ,  H01L23/522

Abstract: A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.

公开(公告)号：US20250014968A1

公开(公告)日：2025-01-09

申请号：US18888158

申请日：2024-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： SHAOFENG DING ,  JEONG HOON AHN ,  YUN KI CHOI

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/18

Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.

公开(公告)号：US20220278193A1

公开(公告)日：2022-09-01

申请号：US17472771

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： SHAOFENG DING ,  JEONG HOON AHN ,  YUN KI CHOI

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/48 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor substrate including a connection region, a pair of epitaxial patterns provided at the semiconductor substrate, a capacitor disposed between the pair of epitaxial patterns, a middle connection layer on the capacitor, an interconnection layer on the middle connection layer, and a through-via provided under the interconnection layer and penetrating the connection region of the semiconductor substrate. The capacitor includes an upper portion of the semiconductor substrate between the pair of epitaxial patterns, a metal electrode on the upper portion of the semiconductor substrate, and a dielectric pattern disposed between the upper portion of the semiconductor substrate and the metal electrode. The through-via is connected to the capacitor through the interconnection layer and the middle connection layer.

公开(公告)号：US20240105556A1

公开(公告)日：2024-03-28

申请号：US18529096

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： SHAOFENG DING ,  JEONG HOON AHN ,  YUN KI CHOI

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/06 ,  H01L25/18

Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.

公开(公告)号：US20220278024A1

公开(公告)日：2022-09-01

申请号：US17469387

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SHAOFENG DING ,  JEONG HOON AHN ,  YUN KI CHOI

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.

公开(公告)号：US20250006594A1

公开(公告)日：2025-01-02

申请号：US18885913

申请日：2024-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： SHAOFENG DING ,  JEONG HOON AHN ,  YUN KI CHOI

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/18

Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.

公开(公告)号：US20240234490A1

公开(公告)日：2024-07-11

申请号：US18611843

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： SHAOFENG DING ,  JEONG HOON AHN ,  YUN KI CHOI

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L28/92 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223

Abstract: A semiconductor device includes a semiconductor substrate including a connection region, a pair of epitaxial patterns provided at the semiconductor substrate, a capacitor disposed between the pair of epitaxial patterns, a middle connection layer on the capacitor, an interconnection layer on the middle connection layer, and a through-via provided under the interconnection layer and penetrating the connection region of the semiconductor substrate. The capacitor includes an upper portion of the semiconductor substrate between the pair of epitaxial patterns, a metal electrode on the upper portion of the semiconductor substrate, and a dielectric pattern disposed between the upper portion of the semiconductor substrate and the metal electrode. The through-via is connected to the capacitor through the interconnection layer and the middle connection layer.

公开(公告)号：US20230260893A1

公开(公告)日：2023-08-17

申请号：US17975002

申请日：2022-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIHYUNG KIM ,  JAEHEE OH ,  JEGWAN HWANG ,  SHAOFENG DING ,  WON JI PARK ,  JEONG HOON AHN ,  YUN KI CHOI

IPC: H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0886 ,  H01L29/7851 ,  H01L29/66795

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; a transistor provided on the first surface of the semiconductor substrate; a power rail provided on the first surface of the semiconductor substrate and electrically connected to the transistor; first and second lower interconnection lines provided on the second surface of the semiconductor substrate and spaced apart from each other in a first direction perpendicular to the second surface of the semiconductor substrate; a penetration via penetrating the semiconductor substrate and connecting a corresponding one of the first and second lower interconnection lines to the power rail; and a capacitor provided between and electrically connected to the first and second lower interconnection lines.