公开(公告)号：US20210257369A1

公开(公告)日：2021-08-19

申请号：US17313570

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/108 ,  G11C11/402

Abstract: A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

公开(公告)号：US11035583B2

公开(公告)日：2021-06-15

申请号：US15992699

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin Kim ,  Ju-Hyun Kang ,  Young-Jae Kim ,  Byung Yul So ,  Yong-Gak Kim ,  In-Jung Baek ,  Na Yeong Byeon ,  Moo Gyo Seo ,  Hyeong Joon Seo ,  Seung Cheon Yu ,  Sang Woo Lee ,  Hyo Kyu Lee ,  Jin Ho Lim ,  Min-Gi Cho ,  Hyeong Kyu Cho ,  Jun Hwang ,  Do Yeon Kim ,  Hyun Ah Kim ,  Yong Ho Seo ,  Woo Seog Song ,  Hyun-Joo Song ,  Young Sun Shin ,  Joon-Ho Yoon ,  Bu Youn Lee ,  Jung Dae Lee ,  Chang Seon Lee ,  Min Gu Jeon ,  Hee Jae Jeong

IPC: F24F11/30 ,  F24F1/0047 ,  F24F1/0057 ,  F24F11/79 ,  F24F11/77 ,  F24F1/0011 ,  F24F1/0022 ,  F24F1/0033 ,  F24F13/24 ,  F24F13/28 ,  F24F110/00 ,  F24F110/10 ,  F24F120/12 ,  F24F11/65 ,  F24F11/41 ,  F24F11/52

Abstract: An air conditioner includes a housing having a suction port and a discharge port, a main fan configured to draw air into the housing through the suction port and discharge air from the housing through the discharge port, an auxiliary fan configured to draw, into the housing, air discharged by the main fan and a controller configured to control a rotational speed of the auxiliary fan to change a direction in which air is discharged from the housing.

公开(公告)号：US11901356B2

公开(公告)日：2024-02-13

申请号：US16817069

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungha Oh ,  Pil-Kyu Kang ,  Kughwan Kim ,  Weonhong Kim ,  Yuichiro Sasaki ,  Sang Woo Lee ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun

IPC: H01L27/06 ,  H01L23/48 ,  H10B41/60 ,  H10B43/20 ,  H10B63/00

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H10B41/60 ,  H10B43/20 ,  H10B63/30 ,  H10B63/84

Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).

公开(公告)号：US11862476B2

公开(公告)日：2024-01-02

申请号：US17076025

申请日：2020-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L21/34 ,  H10B12/00 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/34 ,  H01L21/02 ,  H01L21/28 ,  H10B12/053 ,  H10B12/31 ,  H10B12/482

Abstract: A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

公开(公告)号：US20190296018A1

公开(公告)日：2019-09-26

申请号：US16185892

申请日：2018-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/108

Abstract: A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

公开(公告)号：US11532707B2

公开(公告)日：2022-12-20

申请号：US16796273

申请日：2020-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Bin Song ,  Sang Woo Lee ,  Min Hee Cho

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/51 ,  H01L29/417 ,  H01L29/45 ,  H01L29/24 ,  H01L29/267

Abstract: Aspects of the present inventive concept provide a semiconductor device capable of enhancing performance and reliability through source/drain engineering in a transistor including an oxide semiconductor layer. The semiconductor device includes a substrate, a metal oxide layer disposed on the substrate, a source/drain pattern being in contact with the metal oxide layer and including a portion protruding from a top surface of the metal oxide layer, a plurality of gate structures disposed on the metal oxide layer with the source/drain pattern interposed therebetween and each including gate spacers and an insulating material layer, the insulating material layer being in contact with the metal oxide layer, and not extending along a top surface of the source/drain pattern, and a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern.

公开(公告)号：US11488956B2

公开(公告)日：2022-11-01

申请号：US17313570

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/10 ,  H01L27/108 ,  G11C11/402

Abstract: A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

公开(公告)号：US20210057417A1

公开(公告)日：2021-02-25

申请号：US17076025

申请日：2020-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/108

Abstract: A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

公开(公告)号：US10854612B2

公开(公告)日：2020-12-01

申请号：US16185892

申请日：2018-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/108

Abstract: A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

公开(公告)号：US10410931B2

公开(公告)日：2019-09-10

申请号：US15837613

申请日：2017-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Gil Kang ,  Hyun Seung Song ,  Sang Woo Lee

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/423

Abstract: A fabricating method of a nanosheet transistor includes: forming a plurality of sacrificial layers and a plurality of channel layers on a substrate, wherein the sacrificial layers and the channel layers are alternately arranged; forming a plurality of gates on an uppermost channel layer, wherein the gates are spaced apart from each other; forming a mask on each of the gates; selectively etching the sacrificial layers between the gates, wherein the sacrificial layers between the gates are removed by the etching; depositing a spacer material along sidewalls of the gates and in areas from which the sacrificial layers have been removed; and etching the spacer material to form sidewall spacers along the sidewalls of the gates and inner spacers between the channel layers.