公开(公告)号：US20240074303A1

公开(公告)日：2024-02-29

申请号：US18163504

申请日：2023-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonghyuk Kim ,  Taegon Kim ,  Shinae Jun ,  Hyeonho Choi ,  Seungyeon Kwak ,  Jiwhan Kim ,  Sunghun Lee

IPC: H10K85/30 ,  C09K11/02 ,  C09K11/06 ,  C09K11/08 ,  C09K11/88 ,  H10K50/115 ,  H10K50/12 ,  H10K59/10 ,  H10K85/60

CPC classification number: H10K85/346 ,  C09K11/02 ,  C09K11/06 ,  C09K11/0883 ,  C09K11/883 ,  H10K50/115 ,  H10K50/121 ,  H10K59/10 ,  H10K85/6572 ,  H10K85/658 ,  B82Y20/00

Abstract: A display apparatus, including a substrate including at least one blue light-emitting unit, and a color control portion provided on the substrate and configured to control a color of a light generated at the substrate, wherein the color control portion includes a first color control element, wherein the first color control element includes a first quantum dot for green light conversion, and the at least one blue light-emitting unit of the substrate includes an emission layer, wherein the emission layer includes a host, a first dopant, and a second dopant, and wherein the display apparatus further satisfies conditions as defined herein.

公开(公告)号：US11881508B2

公开(公告)日：2024-01-23

申请号：US17843105

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin Choi ,  Hyunchul Song ,  Sunjung Kim ,  Taegon Kim ,  Seong Hoon Jeong

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H10B10/00 ,  H01L21/308 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L29/0653 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0847 ,  H10B10/12 ,  H01L21/02208 ,  H01L21/308 ,  H01L21/823821 ,  H01L29/6656 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

公开(公告)号：US09553119B2

公开(公告)日：2017-01-24

申请号：US14849187

申请日：2015-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Young Choi ,  Taegon Kim ,  JunHyun Cho

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14614 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14638 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/14698

Abstract: Methods of forming an image sensor are provided. A method of forming an image sensor includes forming a trench in a substrate to define a unit pixel region of the substrate. The method includes forming an in-situ-doped passivation layer on an exposed surface of the trench. The method includes forming a capping pattern on the in-situ-doped passivation layer, in the trench. The method includes forming a photoelectric conversion region in the unit pixel region. Moreover, the method includes forming a floating diffusion region in the unit pixel region.

Abstract translation: 提供了形成图像传感器的方法。 形成图像传感器的方法包括在衬底中形成沟槽以限定衬底的单位像素区域。 该方法包括在沟槽的暴露表面上形成原位掺杂的钝化层。 该方法包括在沟槽中的原位掺杂钝化层上形成封盖图案。 该方法包括在单位像素区域中形成光电转换区域。 此外，该方法包括在单位像素区域中形成浮动扩散区域。

公开(公告)号：US20160079288A1

公开(公告)日：2016-03-17

申请号：US14849187

申请日：2015-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Young Choi ,  Taegon Kim ,  JunHyun Cho

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14614 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14638 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/14698

Abstract: Methods of forming an image sensor are provided. A method of forming an image sensor includes forming a trench in a substrate to define a unit pixel region of the substrate. The method includes forming an in-situ-doped passivation layer on an exposed surface of the trench. The method includes forming a capping pattern on the in-situ-doped passivation layer, in the trench. The method includes forming a photoelectric conversion region in the unit pixel region. Moreover, the method includes forming a floating diffusion region in the unit pixel region.

Abstract translation: 提供了形成图像传感器的方法。 形成图像传感器的方法包括在衬底中形成沟槽以限定衬底的单位像素区域。 该方法包括在沟槽的暴露表面上形成原位掺杂的钝化层。 该方法包括在沟槽中的原位掺杂钝化层上形成封盖图案。 该方法包括在单位像素区域中形成光电转换区域。 此外，该方法包括在单位像素区域中形成浮动扩散区域。

公开(公告)号：US20130171744A1

公开(公告)日：2013-07-04

申请号：US13715099

申请日：2012-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-HOON KANG ,  Taegon Kim ,  Hanmei Choi ,  Eunyoung Jo ,  Gonsu Kang ,  Sungho Kang ,  Sungho Heo

IPC: H01L21/324

CPC classification number: H01L21/324 ,  H01L21/67115 ,  H01L21/67288 ,  H01L21/681 ,  H01L22/10 ,  H01L22/12 ,  H01L22/20

Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.

Abstract translation: 一种热处理晶片的方法包括将晶片装载到具有一个或多个均匀温度梯度区域和一个或多个不均匀温度梯度区域的处理室中。 在晶片中检测到缺陷。 将晶片对准以将缺陷定位在均匀温度梯度的一个或多个区域之一内。 在处理室中的晶片上执行快速热处理，同时将缺陷定位在均匀温度梯度的一个或多个区域之一内。

公开(公告)号：US11837645B2

公开(公告)日：2023-12-05

申请号：US18085871

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoontae Hwang ,  Wandon Kim ,  Geunwoo Kim ,  Heonbok Lee ,  Taegon Kim ,  Hanki Lee

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L23/532 ,  H01L23/485 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L21/285

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76859 ,  H01L21/76886 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

公开(公告)号：US11380760B2

公开(公告)日：2022-07-05

申请号：US17028042

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin Choi ,  Hyunchul Song ,  Sunjung Kim ,  Taegon Kim ,  Seong Hoon Jeong

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/08 ,  H01L21/308 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

公开(公告)号：US10222486B2

公开(公告)日：2019-03-05

申请号：US15174029

申请日：2016-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongchul Kim ,  Taegon Kim ,  Sangeui Lee

IPC: C09K11/61 ,  G01T1/20

Abstract: Provided are a radiation detector and a radiographic apparatus including the same. The radiation detector may have high quantum efficiency due to use of a plurality of nano-waveguides that extend from an incident end thereof to an exit end thereof and are configured to generate scintillation as radiation rays penetrate therethrough or a photoconductor.

公开(公告)号：US09443932B2

公开(公告)日：2016-09-13

申请号：US14330777

申请日：2014-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Chul Kim ,  Joonghan Shin ,  Bongjin Kuh ,  Taegon Kim ,  Hanmei Choi

IPC: H01L21/70 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/0696 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1211

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a plurality of unit cells provided on a semiconductor substrate. Each of the unit cells may include a buried insulating pattern buried in the semiconductor substrate, a first active pattern provided on the buried insulating pattern, and a second active pattern provided on the buried insulating pattern and spaced apart from the first active pattern. The buried insulating pattern may define a unit cell region, in which each of the unit cells may be disposed.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括设置在半导体衬底上的多个单元电池。 每个单电池可以包括埋在半导体衬底中的掩埋绝缘图案，设置在掩埋绝缘图案上的第一有源图案和设置在掩埋绝缘图案上并与第一有源图案间隔开的第二有源图案。 埋置的绝缘图案可以限定单位单元区域，其中可以布置每个单位单元。

公开(公告)号：US11322494B2

公开(公告)日：2022-05-03

申请号：US17015307

申请日：2020-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Taehyeon Kim ,  Hongshik Shin ,  Taegon Kim ,  Jaeyoung Park ,  Yuichiro Sasaki

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/225 ,  H01L29/161 ,  H01L29/165 ,  H01L21/285

Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.