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    Fast transversal multi-input system
    3.
    发明授权
    Fast transversal multi-input system 有权
    快速横向多输入系统

    公开(公告)号：US09407472B1

    公开(公告)日：2016-08-02

    申请号：US14308461

    申请日：2014-06-18

    Applicant: Seagate Technology LLC

    Inventor： Belkacem Derras ,  William Michael Radich ,  Rishi Ahuja

    IPC: H03H7/30 ,  H04L25/03

    CPC classification number: H04L25/03891 ,  H04L25/03019 ,  H04L2025/03426 ,  H04L2025/03649

    Abstract: Multiple input single output (MISO) systems and processes are presented that can adaptively equalize multiple signals to produce an output. In some examples, the MISO systems can include a fast transversal recursive least square (RLS) algorithm to produce the output. Fast transversal RLS algorithms can be less complex than other RLS algorithms. In some examples, the fast transversal RLS algorithm may be optimized to have no division operations. The MISO system may have two or more inputs.

    Abstract translation: 提出了多输入单输出（MISO）系统和过程，其可以自适应地均衡多个信号以产生输出。 在一些示例中，MISO系统可以包括快速的横向递归最小二乘法（RLS）算法来产生输出。 快速横向RLS算法可能不如其他RLS算法复杂。 在一些示例中，快速横向RLS算法可以被优化为不具有除法运算。 MISO系统可以具有两个或更多个输入。

    Blind partial response equalization
    4.
    发明授权
    Blind partial response equalization 有权

    公开(公告)号：US10069653B1

    公开(公告)日：2018-09-04

    申请号：US15594140

    申请日：2017-05-12

    Applicant: Seagate Technology LLC

    Inventor： Belkacem Derras

    IPC: H04L25/03

    Abstract: An equalizer and an equalization method. The method includes receiving a data signal over a channel. The method further includes equalizing the data signal, by a blind partial response equalizer circuit, to provide an equalized output of the data signal. An estimation of partial response equalizer taps employed to determine the equalized output, by the blind partial response equalizer circuit, is carried out independently of true channel input symbols and detected symbols corresponding to the data signal.

    TIMING ERROR PROCESSOR THAT USES THE DERIVATIVE OF AN INTERPOLATOR FUNCTION
    5.
    发明申请
    TIMING ERROR PROCESSOR THAT USES THE DERIVATIVE OF AN INTERPOLATOR FUNCTION 有权
    时间误差处理器使用插值函数的衍生物

    公开(公告)号：US20160344540A1

    公开(公告)日：2016-11-24

    申请号：US14720568

    申请日：2015-05-22

    Applicant: Seagate Technology LLC

    Inventor： Belkacem Derras ,  Raman Venkataramani ,  William Michael Radich

    IPC: H04L7/04 ,  H04L7/027 ,  H04L27/227

    CPC classification number: H04L7/048 ,  G11B20/10009 ,  H04L7/0029 ,  H04L7/0062 ,  H04L7/027 ,  H04L25/03 ,  H04L27/2271

    Abstract: A digitized signal is processed via an interpolator. The interpolator performs timing adjustment on the digitized signal. The error signal is determined based on a desired signal and the time-adjusted digitized signal. A corrective phase shift of the digitized signal is determined via a least-mean-squared processing block that uses the error and the derivative of a function used by the interpolator. The corrective phase shift is input to the interpolator to perform the timing adjustment.

    Abstract translation: 通过内插器处理数字化信号。 内插器对数字化信号执行定时调整。 误差信号根据期望的信号和时间调整的数字化信号确定。 数字化信号的校正相移通过使用误差的内插器所使用的函数的导数的最小均方处理块来确定。 校正相移被输入到内插器以执行定时调整。

    Track interference cancellation
    6.
    发明授权
    Track interference cancellation 有权
    跟踪干扰消除

    公开(公告)号：US09093115B1

    公开(公告)日：2015-07-28

    申请号：US14471703

    申请日：2014-08-28

    Applicant: Seagate Technology LLC

    Inventor： Kendall Hayne Fung ,  David H. Dahlem, Jr. ,  Raman Chatapuram Vankataramani ,  Belkacem Derras ,  William Michael Radich

    IPC: G11B21/02 ,  G11B27/36 ,  G11B20/10 ,  G11B5/09

    CPC classification number: G11B20/10046 ,  G11B5/09

    Abstract: A system can include a first buffer storing a first fragment of data for a first data sector in a first track of a storage medium, a second buffer storing a second fragment of data for a second data sector in a second track of the storage medium adjacent to the first track, a processor configured to determine an estimated region of overlap between the first data fragment and the second data fragment, and a circuit configured to refine the estimated region of overlap by determining an offset value to offset an estimated beginning portion of overlap by the second fragment.

    Abstract translation: 系统可以包括第一缓冲器，其存储用于存储介质的第一轨道中的第一数据扇区的第一数据片段;存储第二数据扇区的第二数据片段的第二缓冲器，所述第二数据段在相邻的存储介质的第二轨道中 第一轨道，被配置为确定所述第一数据片段和所述第二数据片段之间的重叠的估计区域的处理器，以及被配置为通过确定偏移值来精细化所述估计的重叠区域的电路，以偏移估计的重叠开始部分 由第二个片段。

    Interleaving code-words
    8.
    发明授权
    Interleaving code-words 有权

    公开(公告)号：US09654145B1

    公开(公告)日：2017-05-16

    申请号：US14552207

    申请日：2014-11-24

    Applicant: Seagate Technology LLC

    Inventor： Belkacem Derras ,  Deepak Sridhara ,  Richard Parshall

    IPC: G06F11/10 ,  H03M13/27

    CPC classification number: G06F11/1048 ,  H03M13/2789

    Abstract: A storage device disclosed herein includes a memory and a write channel configured to interleave a plurality of code-words to generate a plurality of multiplet sequences such that at least two of the plurality of code-words interleave to the end of the interleaving process. In one example implementation, for each of the multiplet sequences no two successive multiplets are from the same code-word, a multiplet including a plurality of bits from a single code-word.

    PHASE ERROR RECOVERY CIRCUITRY AND METHOD FOR A MAGNETIC RECORDING DEVICE
    10.
    发明申请
    PHASE ERROR RECOVERY CIRCUITRY AND METHOD FOR A MAGNETIC RECORDING DEVICE 有权
    相位误差恢复电路和磁记录装置的方法

    公开(公告)号：US20170025147A1

    公开(公告)日：2017-01-26

    申请号：US14808721

    申请日：2015-07-24

    Applicant: Seagate Technology LLC

    Inventor： Michael J. Link ,  Bruce Douglas Buch ,  Belkacem Derras

    IPC: G11B20/10 ,  G11B20/18 ,  G11B5/09

    CPC classification number: G11B20/1024 ,  G11B5/09 ,  G11B20/1816 ,  G11B2005/0021 ,  G11B2020/183

    Abstract: A recording head is configured to write and read data sectors to and from a recording medium, such as a heat-assisted recording medium. A read channel is coupled to the recording head. Phase-locked loop (PLL) circuitry of the read channel is configured to detect a change in a phase error at a location of the data sector. The phase error change may be indicative of a mode-hop that occurred while writing the data sector to the medium. The PLL circuitry is configured to determine a phase offset using the phase error. A controller is configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.

    Abstract translation: 记录头被配置为向诸如热辅助记录介质的记录介质写入和读取数据扇区。 读通道耦合到记录头。 读通道的锁相环（PLL）电路被配置为检测数据扇区位置处的相位误差的变化。 相位误差变化可以指示在将数据扇区写入介质时发生的模式跳跃。 PLL电路被配置为使用相位误差来确定相位偏移。 控制器被配置为使用相位偏移来重新读取数据扇区位置，以恢复数据扇区位置。

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