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公开(公告)号：US20220393089A1
公开(公告)日：2022-12-08
申请号：US17337394
申请日：2021-06-02
Applicant: SeeQC, Inc.
Inventor： Daniel Yohannes , Mario Renzullo , John Vivalda , Alexander Kirichenko
Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.
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公开(公告)号：US11508896B1
公开(公告)日：2022-11-22
申请号：US17337394
申请日：2021-06-02
Applicant: SeeQC, Inc.
Inventor： Daniel Yohannes , Mario Renzullo , John Vivalda , Alexander Kirichenko
Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.
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公开(公告)号：US11991935B2
公开(公告)日：2024-05-21
申请号：US17990864
申请日：2022-11-21
Applicant: SeeQC Inc.
Inventor： Daniel Yohannes , Mario Renzullo , John Vivalda , Alexander Kirichenko
CPC classification number: H10N60/84 , G11C11/44 , H10N60/12 , H10N60/805 , H10N69/00
Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.
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公开(公告)号：US20230337553A1
公开(公告)日：2023-10-19
申请号：US17990864
申请日：2022-11-21
Applicant: SeeQC Inc.
Inventor： Daniel Yohannes , Mario Renzullo , John Vivalda , Alexander Kirichenko
IPC: G11C11/44
CPC classification number: H10N60/84 , H10N60/12 , H10N69/00 , G11C11/44 , H10N60/805
Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.
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