-
公开(公告)号：US11747196B1
公开(公告)日：2023-09-05
申请号：US17862276
申请日：2022-07-11
Applicant: SeeQC, Inc.
Inventor： Amir Jafari-Salim , Daniel Yohannes , Oleg A. Mukhanov , Alan M. Kadin
CPC classification number: G01J1/44 , G01J1/0425 , G06F1/10 , H10N60/84 , G01J2001/442
Abstract: Superconducting nanowire single photon detectors have recently been developed for a wide range of applications, including imaging and communications. An improved detection system is disclosed, whereby the detectors are monolithically integrated on the same chip with Josephson junctions for control and data processing. This enables an enhanced data rate, thereby facilitating several new and improved applications. A preferred embodiment comprises integrated digital processing based on single-flux-quantum pulses. An integrated multilayer fabrication method for manufacturing these integrated detectors is also disclosed. Preferred examples of systems comprising such integrated nanowire photon detectors include a time-correlated single photon counter, a quantum random number generator, an integrated single-photon imaging array, a sensitive digital communication receiver, and quantum-key distribution for a quantum communication system.
-
公开(公告)号：US20230380302A1
公开(公告)日：2023-11-23
申请号：US18357814
申请日：2023-07-24
Applicant: SeeQC, Inc.
Inventor： Daniel Yohannes , Denis Amparo , Oleksandr Chernyashevskyy , Oleg Mukhanov , Mario Renzullo , Andrei Talalaeskii , Igor Vernik , John Vivalda , Jason Walter
CPC classification number: H10N60/815 , H01L24/13 , H01L24/81 , H01L24/05 , H10N60/12 , H10N60/0912 , H01L2924/0495 , H01L2224/0401 , H01L2224/05179 , H01L2224/13083 , H01L2224/13109 , H01L2224/13147 , H01L2224/13166 , H01L2224/13179 , H01L2224/8109 , H01L2224/8112 , H01L2224/81203 , H01L2924/04941
Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.
-
公开(公告)号：US20220393089A1
公开(公告)日：2022-12-08
申请号：US17337394
申请日：2021-06-02
Applicant: SeeQC, Inc.
Inventor： Daniel Yohannes , Mario Renzullo , John Vivalda , Alexander Kirichenko
Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.
-
公开(公告)号：US11508896B1
公开(公告)日：2022-11-22
申请号：US17337394
申请日：2021-06-02
Applicant: SeeQC, Inc.
Inventor： Daniel Yohannes , Mario Renzullo , John Vivalda , Alexander Kirichenko
Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.
-
公开(公告)号：US11121302B2
公开(公告)日：2021-09-14
申请号：US16599985
申请日：2019-10-11
Applicant: SeeQC, Inc.
Inventor： Daniel Yohannes , Denis Amparo , Oleksandr Chernyashevskyy , Oleg Mukhanov , Mario Renzullo , Andrei Talalaeskii , Igor Vernik , John Vivalda , Jason Walter
Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.
-
Patent Agency Ranking
公开(公告)号：US12098949B1
公开(公告)日：2024-09-24
申请号：US18241816
申请日：2023-09-01
Applicant: SeeQC, Inc.
Inventor： Amir Jafari-Salim , Daniel Yohannes , Oleg A. Mukhanov , Alan M. Kadin
CPC classification number: G01J1/44 , G01J1/0425 , G06F1/10 , H10N60/84 , G01J2001/442
Abstract: Superconducting nanowire single photon detectors have recently been developed for a wide range of applications, including imaging and communications. An improved detection system is disclosed, whereby the detectors are monolithically integrated on the same chip with Josephson junctions for control and data processing. This enables an enhanced data rate, thereby facilitating several new and improved applications. A preferred embodiment comprises integrated digital processing based on single-flux-quantum pulses. An integrated multilayer fabrication method for manufacturing these integrated detectors is also disclosed. Preferred examples of systems comprising such integrated nanowire photon detectors include a time-correlated single photon counter, a quantum random number generator, an integrated single-photon imaging array, a sensitive digital communication receiver, and quantum-key distribution for a quantum communication system.
-
公开(公告)号：US11991935B2
公开(公告)日：2024-05-21
申请号：US17990864
申请日：2022-11-21
Applicant: SeeQC Inc.
Inventor： Daniel Yohannes , Mario Renzullo , John Vivalda , Alexander Kirichenko
CPC classification number: H10N60/84 , G11C11/44 , H10N60/12 , H10N60/805 , H10N69/00
Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.
-
公开(公告)号：US20230337553A1
公开(公告)日：2023-10-19
申请号：US17990864
申请日：2022-11-21
Applicant: SeeQC Inc.
Inventor： Daniel Yohannes , Mario Renzullo , John Vivalda , Alexander Kirichenko
IPC: G11C11/44
CPC classification number: H10N60/84 , H10N60/12 , H10N69/00 , G11C11/44 , H10N60/805
Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.
-
公开(公告)号：US11711985B2
公开(公告)日：2023-07-25
申请号：US17472821
申请日：2021-09-13
Applicant: SeeQC, Inc.
Inventor： Daniel Yohannes , Denis Amparo , Oleksandr Chernyashevskyy , Oleg Mukhanov , Mario Renzullo , Andrei Talalaevskii , Igor Vernik , John Vivalda , Jason Walter
IPC: H01L29/06 , H01L29/08 , H01L31/0256 , H01L39/22 , H10N60/81 , H01L23/00 , H10N60/12 , H10N60/01
CPC classification number: H10N60/815 , H01L24/05 , H01L24/13 , H01L24/81 , H10N60/0912 , H10N60/12 , H01L2224/0401 , H01L2224/05179 , H01L2224/13083 , H01L2224/13109 , H01L2224/13147 , H01L2224/13166 , H01L2224/13179 , H01L2224/8109 , H01L2224/8112 , H01L2224/81203 , H01L2924/0495 , H01L2924/04941
Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.
-
公开(公告)号：US20220237495A1
公开(公告)日：2022-07-28
申请号：US17501897
申请日：2021-10-14
Applicant: SeeQC, Inc.
Inventor： Daniel Yohannes , Igor Vernik , Caleb Jordan , Patrick Truitt , Alex Kirichenko , Amir Jafari Salim , Naveen Katam , Oleg Mukhanov
Abstract: The technology disclosed in this patent document can be implemented to combine quantum computing, classical qubit control/readout, and classical digital computing in a scalable computing system based on superconducting qubits and special interconnection designs for connecting hardware components within a multi-stage cryogenic system to provide fast communications between the quantum computing module and its controller while allowing efficient management of wiring with other modules.
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.016 seconds)
