PHOSPHORUS AND ARSENIC DOPING OF SEMICONDUCTOR MATERIALS
    1.
    发明申请
    PHOSPHORUS AND ARSENIC DOPING OF SEMICONDUCTOR MATERIALS 审中-公开
    半导体材料的磷和砷的掺杂

    公开(公告)号:US20150111372A1

    公开(公告)日:2015-04-23

    申请号:US14519250

    申请日:2014-10-21

    Applicant: Sematech, Inc.

    CPC classification number: H01L21/2254 H01L21/2225 H01L21/228

    Abstract: Provided are methods for preparing a doped silicon material. The methods include contacting a surface of a silicon material with a dopant solution comprising a dopant-containing compound selected from a phosphorus-containing compound and an arsenic-containing compound, to form a layer of dopant material on the surface; and diffusing the dopant into the silicon material, thereby forming the doped silicon material, wherein the doped silicon material has a sheet resistance (Rs) of less than or equal to 2,000 Ω/sq.

    Abstract translation: 提供了制备掺杂硅材料的方法。 所述方法包括使硅材料的表面与包含选自含磷化合物和含砷化合物的掺杂剂化合物的掺杂剂溶液接触,以在表面上形成掺杂剂材料层; 并将掺杂剂扩散到硅材料中,从而形成掺杂的硅材料,其中掺杂硅材料的薄层电阻(Rs)小于或等于2,000&OHgr / sq。

    METAL ALLOY WITH AN ABRUPT INTERFACE TO III-V SEMICONDUCTOR
    2.
    发明申请
    METAL ALLOY WITH AN ABRUPT INTERFACE TO III-V SEMICONDUCTOR 有权
    金属合金与III-V半导体的ABRUPT接口

    公开(公告)号:US20140183597A1

    公开(公告)日:2014-07-03

    申请号:US13729592

    申请日:2012-12-28

    Applicant: SEMATECH, INC.

    Abstract: Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.

    Abstract translation: 具有包括n型III-V半导体材料的第一层和包括M(InP)(InGaAs)合金)的第二层的半导体结构,其中M选自Ni,Pt,Pd,Co,Ti,Zr,Y, Mo,Ru,Ir,Sb,In,Dy,Tb,Er,Yb和Te及其组合。 半导体结构在第一和第二层之间具有基本平坦的界面。 还公开了制造半导体结构的方法,以及降低接触面的界面粗糙度和/或薄层电阻的方法。

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