公开(公告)号：US20250123715A1

公开(公告)日：2025-04-17

申请号：US18888359

申请日：2024-09-18

Applicant: Sharp Display Technology Corporation

Inventor： Seiya KAWAMORITA ,  Satoshi HORIUCHI ,  Yasuaki IWASE ,  Shinji MATSUBARA

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/20 ,  G11C19/28

Abstract: A drive circuit comprising a plurality of stages comprises a latch circuit configured to retain an output signal inputted from a preceding stage in a suspension period in which the drive circuit is suspended and configured to supply the output signal to a succeeding stage when the suspension period ends, the latch circuit includes a signal retaining node; a first transistor including a first electrode supplied a first control signal when the suspension period ends and a first control electrode; a second output node connected to the first control electrode; and a second transistor including a second control electrode supplied a second control signal supplied after the suspension period starts, but before the first control signal is supplied to the first electrode, the second transistor electrically connects the signal retaining node and the second output node by the second control signal supplied to the second control electrode.

公开(公告)号：US20240194151A1

公开(公告)日：2024-06-13

申请号：US18504299

申请日：2023-11-08

Applicant: Sharp Display Technology Corporation

Inventor： Seiya KAWAMORITA ,  Satoshi HORIUCHI ,  Yasuaki IWASE

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08

Abstract: A unit circuit constituting each of stages of a shift register is provided with a thin film transistor, the thin film transistor including a control terminal applied with one of a plurality of gate clock signals, a first conduction terminal connected to a third node, and a second conduction terminal applied with a direct current power supply voltage of a low level. The third node is connected to a control terminal of a thin film transistor configured to change a potential of a second node toward a high level. When a gate clock signal applied to a control terminal of a thin film transistor configured to change a potential of the third node toward the high level changes from the high level to the low level, the gate clock signal applied to the control terminal of the thin film transistor changes from the low level to the high level.

公开(公告)号：US20240105139A1

公开(公告)日：2024-03-28

申请号：US18236906

申请日：2023-08-22

Applicant: Sharp Display Technology Corporation

Inventor： Satoshi HORIUCHI ,  Akane SUGISAKA ,  Seiya KAWAMORITA ,  Shinji MATSUBARA

IPC: G09G3/36 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G09G3/3677 ,  G02F1/136286 ,  G02F1/1368 ,  G09G2310/08

Abstract: Provided is a display device including gate drive circuits, a signal line connected to the gate drive circuit, a signal line connected to the gate drive circuit, a gate terminal, inspection terminals, and a connection line. The connection line connects the signal line and the signal line. The inspection terminal is disposed on the signal line. The inspection terminal is disposed on the signal line. The inspection terminals are terminals input with an inspection signal at the time of inspection.