公开(公告)号：US20250123716A1

公开(公告)日：2025-04-17

申请号：US18892844

申请日：2024-09-23

Applicant: Sharp Display Technology Corporation

Inventor： Yasuaki IWASE ,  Seijirou GYOUTEN ,  Satoshi HORIUCHI ,  Shinji MATSUBARA

IPC: G06F3/041 ,  G02F1/1333 ,  G06F3/044 ,  G09G3/36

Abstract: A drive circuit includes a plurality of stages and configured to supply a drive signal to a scanning signal line group in response to input of a plurality of clock signals. The drive circuit includes a plurality of unit circuits respectively constituting the plurality of stages, the plurality of unit circuits being configured to output the drive signal, a latch circuit provided in parallel with the plurality of unit circuits, and a connection circuit connected to an output node of the latch circuit.

公开(公告)号：US20240194151A1

公开(公告)日：2024-06-13

申请号：US18504299

申请日：2023-11-08

Applicant: Sharp Display Technology Corporation

Inventor： Seiya KAWAMORITA ,  Satoshi HORIUCHI ,  Yasuaki IWASE

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08

Abstract: A unit circuit constituting each of stages of a shift register is provided with a thin film transistor, the thin film transistor including a control terminal applied with one of a plurality of gate clock signals, a first conduction terminal connected to a third node, and a second conduction terminal applied with a direct current power supply voltage of a low level. The third node is connected to a control terminal of a thin film transistor configured to change a potential of a second node toward a high level. When a gate clock signal applied to a control terminal of a thin film transistor configured to change a potential of the third node toward the high level changes from the high level to the low level, the gate clock signal applied to the control terminal of the thin film transistor changes from the low level to the high level.

公开(公告)号：US20220406267A1

公开(公告)日：2022-12-22

申请号：US17750449

申请日：2022-05-23

Applicant: Sharp Display Technology Corporation

Inventor： Yohei TAKEUCHI ,  Akira TAGAWA ,  Yasuaki IWASE ,  Jun NISHIMURA

IPC: G09G3/36

Abstract: A light control panel including an image display region including a region corresponding to an image display region in a display panel and a region corresponding to a peripheral circuit region in the display panel is provided between the display panel and a backlight. A pattern image for controlling radiation of light emitted from the backlight to the display panel is displayed in the image display region in the light control panel according to an action state of the peripheral circuit in the display panel.

公开(公告)号：US20220373832A1

公开(公告)日：2022-11-24

申请号：US17743517

申请日：2022-05-13

Applicant: Sharp Display Technology Corporation

Inventor： Jun NISHIMURA ,  Akira TAGAWA ,  Yasuaki IWASE ,  Yohei TAKEUCHI

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1343

Abstract: An active matrix substrate includes a first pixel region defined by first and second source bus lines adjacent to each other and first and second gate bus lines adjacent to each other and further includes a first pixel electrode and a first oxide semiconductor TFT that are associated with the first pixel region. The first oxide semiconductor TFT includes an oxide semiconductor layer and a gate electrode electrically connected to the first gate bus line. The oxide semiconductor layer includes a channel region and a low-resistance region including first and second regions located on opposite sides of the channel region. When viewed in a direction normal to the substrate, the low-resistance region extends across the first source bus line to another pixel region and partially overlaps a pixel electrode disposed in the other pixel region with an insulating layer interposed therebetween.

公开(公告)号：US20250123715A1

公开(公告)日：2025-04-17

申请号：US18888359

申请日：2024-09-18

Applicant: Sharp Display Technology Corporation

Inventor： Seiya KAWAMORITA ,  Satoshi HORIUCHI ,  Yasuaki IWASE ,  Shinji MATSUBARA

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/20 ,  G11C19/28

Abstract: A drive circuit comprising a plurality of stages comprises a latch circuit configured to retain an output signal inputted from a preceding stage in a suspension period in which the drive circuit is suspended and configured to supply the output signal to a succeeding stage when the suspension period ends, the latch circuit includes a signal retaining node; a first transistor including a first electrode supplied a first control signal when the suspension period ends and a first control electrode; a second output node connected to the first control electrode; and a second transistor including a second control electrode supplied a second control signal supplied after the suspension period starts, but before the first control signal is supplied to the first electrode, the second transistor electrically connects the signal retaining node and the second output node by the second control signal supplied to the second control electrode.