公开(公告)号：US12044943B2

公开(公告)日：2024-07-23

申请号：US17903085

申请日：2022-09-06

Applicant: Sharp Display Technology Corporation

Inventor： Tatsuya Kawasaki ,  Tohru Daitoh ,  Hajime Imai ,  Teruyuki Ueda ,  Masaki Maeda ,  Yoshiharu Hirata ,  Yoshihito Hara

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  G09G3/36 ,  H01L27/12

CPC classification number: G02F1/136286 ,  G02F1/134336 ,  G02F1/136213 ,  G02F1/13685 ,  G09G3/3614 ,  H01L27/1225

Abstract: An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.

公开(公告)号：US12276893B2

公开(公告)日：2025-04-15

申请号：US18416940

申请日：2024-01-19

Applicant: Sharp Display Technology Corporation

Inventor： Yoshihito Hara ,  Tohru Daitoh ,  Hajime Imai ,  Teruyuki Ueda ,  Masaki Maeda ,  Tatsuya Kawasaki ,  Yoshiharu Hirata

IPC: G02F1/1368 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1362 ,  G03F7/00 ,  G06F3/041 ,  G06F3/044

Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer insulating layer, and a pixel electrode electrically connected to the connection electrode in an upper opening formed in the first dielectric layer and the second dielectric layer.

公开(公告)号：US11927860B2

公开(公告)日：2024-03-12

申请号：US17717235

申请日：2022-04-11

Applicant: Sharp Display Technology Corporation

Inventor： Yoshihito Hara ,  Tohru Daitoh ,  Hajime Imai ,  Teruyuki Ueda ,  Masaki Maeda ,  Tatsuya Kawasaki ,  Yoshiharu Hirata

IPC: G02F1/1368 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1362 ,  G03F7/00 ,  G06F3/041 ,  G06F3/044

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/134336 ,  G02F1/13454 ,  G02F1/136286 ,  G03F7/70 ,  G06F3/0412 ,  G02F2201/42 ,  G02F2202/10 ,  G06F3/04164 ,  G06F3/044

Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer insulating layer, and a pixel electrode electrically connected to the connection electrode in an upper opening formed in the first dielectric layer and the second dielectric layer.