公开(公告)号：US12276893B2

公开(公告)日：2025-04-15

申请号：US18416940

申请日：2024-01-19

Applicant: Sharp Display Technology Corporation

Inventor： Yoshihito Hara ,  Tohru Daitoh ,  Hajime Imai ,  Teruyuki Ueda ,  Masaki Maeda ,  Tatsuya Kawasaki ,  Yoshiharu Hirata

IPC: G02F1/1368 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1362 ,  G03F7/00 ,  G06F3/041 ,  G06F3/044

Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer insulating layer, and a pixel electrode electrically connected to the connection electrode in an upper opening formed in the first dielectric layer and the second dielectric layer.

公开(公告)号：US12057085B2

公开(公告)日：2024-08-06

申请号：US18233359

申请日：2023-08-14

Applicant: Sharp Display Technology Corporation

Inventor： Jun Nishimura ,  Kengo Hara ,  Yohei Takeuchi ,  Yoshihito Hara ,  Tohru Daitoh

IPC: G09G3/36 ,  G06F3/041 ,  G09G3/20

CPC classification number: G09G3/3677 ,  G06F3/04166 ,  G09G3/2096 ,  G09G2310/0286 ,  G09G2330/021

Abstract: A set circuit in a unit circuit in a gate driver of a display device includes a setting transistor, a first auxiliary transistor, and a second auxiliary transistor. The setting transistor includes a source terminal connected to an internal node, a gate terminal connected to a set input terminal, and a drain terminal connected to the set input terminal via the first auxiliary transistor and also connected to an input terminal via the second auxiliary transistor in a diode-connected form. Each transistor is controlled to be in an on state and an off state during normal drive and is controlled to be in the off state and the on state during a pause period by a control signal supplied to the input terminal.

公开(公告)号：US12117706B2

公开(公告)日：2024-10-15

申请号：US18407420

申请日：2024-01-08

Applicant: Sharp Display Technology Corporation

Inventor： Kengo Hara ,  Tohru Daitoh ,  Yoshihito Hara ,  Jun Nishimura ,  Yohei Takeuchi

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12

CPC classification number: G02F1/13629 ,  G02F1/1368 ,  H01L27/124

Abstract: An active matrix substrate includes a pixel TFT provided corresponding to each pixel region, a pixel electrode electrically connected to the pixel TFT, a plurality of gate wirings extending in a row direction, and a plurality of source wirings extending in a column direction. Each gate wiring has a multilayer structure including a lower gate wiring electrically connected to a lower gate electrode included in the pixel TFT and an upper gate wiring electrically connected to an upper gate electrode included in the pixel TFT. In a case where the number of the gate wirings is defined as m and the number of the source wirings is defined as n, each gate wiring has 3 or more and less than n contact portions, each contact portion is positioned in any of n intersection regions, and the number of the contact portions overlapping each source wiring is less than m.

公开(公告)号：US11830454B2

公开(公告)日：2023-11-28

申请号：US18101270

申请日：2023-01-25

Applicant: Sharp Display Technology Corporation

Inventor： Kengo Hara ,  Tohru Daitoh ,  Yoshihito Hara ,  Jun Nishimura ,  Yohei Takeuchi

IPC: G09G3/36 ,  H01L27/12

CPC classification number: G09G3/3677 ,  H01L27/124 ,  H01L27/1225 ,  G09G2310/0286 ,  G09G2330/021

Abstract: An active matrix substrate includes a gate driver including a shift register including a plurality of unit circuits connected in multiple stages. Each of the plurality of unit circuits includes an output node, a first node, a first TFT including a first gate terminal supplied with the set signal, a first source terminal connected to the first node, and a first drain terminal supplied with a first power supply potential higher than a low-level potential of the set signal, and a second TFT including a second gate terminal connected to the first node, a second source terminal connected to the output node, and a second drain terminal supplied with the clock signal. The first TFT includes a semiconductor layer, and a first and a second gate electrodes disposed on a side of the semiconductor layer opposite to the substrate and connected to the first gate terminal. The semiconductor layer includes a source contact region electrically connected to the first source terminal, a drain contact region electrically connected to the first drain terminal, and a first and a second channel regions separated from each other in a channel length direction between the contact regions when viewed from a normal direction of the substrate. The first gate electrode overlaps the first channel region via an upper gate insulating layer, and the second gate electrode overlaps the second channel region via the upper gate insulating layer.

公开(公告)号：US20240257774A1

公开(公告)日：2024-08-01

申请号：US18529438

申请日：2023-12-05

Applicant: Sharp Display Technology Corporation

Inventor： Jun NISHIMURA ,  Yoshihito Hara ,  Masaki Maeda ,  Yoshiharu Hirata ,  Hideki Kitagawa ,  Masamitsu Yamanaka ,  Tohru Daitoh

IPC: G09G3/34 ,  G11C19/28

CPC classification number: G09G3/3446 ,  G11C19/28 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08

Abstract: In each of unit circuits that constitute a shift register, a first conduction terminal of a second thin-film transistor that controls the output of an output signal serving as a scanning signal is given a second input clock signal having a amplitude larger than the amplitude of a first input clock signal that is given to a first conduction terminal of a first thin-film transistor that controls the output of an output signal serving as a control signal for controlling another unit circuit. The channel length of the second thin-film transistor is set to be greater than the channel length of the first thin-film transistor, so that the breakdown voltage of the second thin-film transistor is higher than the breakdown voltage of the first thin-film transistor.

公开(公告)号：US11927860B2

公开(公告)日：2024-03-12

申请号：US17717235

申请日：2022-04-11

Applicant: Sharp Display Technology Corporation

Inventor： Yoshihito Hara ,  Tohru Daitoh ,  Hajime Imai ,  Teruyuki Ueda ,  Masaki Maeda ,  Tatsuya Kawasaki ,  Yoshiharu Hirata

IPC: G02F1/1368 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1362 ,  G03F7/00 ,  G06F3/041 ,  G06F3/044

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/134336 ,  G02F1/13454 ,  G02F1/136286 ,  G03F7/70 ,  G06F3/0412 ,  G02F2201/42 ,  G02F2202/10 ,  G06F3/04164 ,  G06F3/044

Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer insulating layer, and a pixel electrode electrically connected to the connection electrode in an upper opening formed in the first dielectric layer and the second dielectric layer.

公开(公告)号：US12125856B2

公开(公告)日：2024-10-22

申请号：US18140593

申请日：2023-04-27

Applicant: Sharp Display Technology Corporation

Inventor： Yoshihito Hara ,  Tohru Daitoh ,  Jun Nishimura ,  Kengo Hara ,  Yohei Takeuchi

IPC: H01L27/12 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G06F3/041 ,  G06F3/044

CPC classification number: H01L27/1248 ,  G02F1/13338 ,  G02F1/133512 ,  G02F1/1337 ,  G02F1/134372 ,  G02F1/136204 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G06F3/0412 ,  G06F3/04164 ,  G06F3/0446

Abstract: An active matrix substrate includes a thin film transistor including an oxide semiconductor layer, an interlayer insulating layer covering the thin film transistor, a pixel electrode provided above the interlayer insulating layer and electrically connected to the thin film transistor, a common electrode provided between the pixel electrode and the interlayer insulating layer, a first dielectric layer provided between the common electrode and the pixel electrode, and an alignment film covering the pixel electrode. The first dielectric layer includes a plurality of openings each of which exposes a part of the common electrode and includes the alignment film positioned therein.

公开(公告)号：US12044943B2

公开(公告)日：2024-07-23

申请号：US17903085

申请日：2022-09-06

Applicant: Sharp Display Technology Corporation

Inventor： Tatsuya Kawasaki ,  Tohru Daitoh ,  Hajime Imai ,  Teruyuki Ueda ,  Masaki Maeda ,  Yoshiharu Hirata ,  Yoshihito Hara

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  G09G3/36 ,  H01L27/12

CPC classification number: G02F1/136286 ,  G02F1/134336 ,  G02F1/136213 ,  G02F1/13685 ,  G09G3/3614 ,  H01L27/1225

Abstract: An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.

公开(公告)号：US11955097B2

公开(公告)日：2024-04-09

申请号：US18075307

申请日：2022-12-05

Applicant: Sharp Display Technology Corporation

Inventor： Jun Nishimura ,  Yoshihito Hara ,  Yohei Takeuchi ,  Kengo Hara ,  Tohru Daitoh

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G11C19/28 ,  G09G2300/0852 ,  G09G2310/0286

Abstract: A shift register includes stages each constituted by a unit circuit provided with a thin-film transistor (separation transistor) that separates a control node into an output-side first control node and an input-side second control node and a capacitor whose first end is connected to the second control node. The thin-film transistor (separation transistor) has a control terminal that is supplied with a high-level DC power supply voltage. Typically, the channel width of a thin-film transistor (first output control transistor) that controls output from a unit circuit is ten or more times greater than the channel width of the thin-film transistor (separation transistor).