公开(公告)号：US10354891B2

公开(公告)日：2019-07-16

申请号：US15945308

申请日：2018-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chih-Jen Yang ,  Yu-Chih Cheng ,  Chee-Key Chung ,  Chang-Fu Lin

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.

公开(公告)号：US20190181021A1

公开(公告)日：2019-06-13

申请号：US15945308

申请日：2018-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chih-Jen Yang ,  Yu-Chih Cheng ,  Chee-Key Chung ,  Chang-Fu Lin

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/568 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/06 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3512

Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.

公开(公告)号：US20220028721A1

公开(公告)日：2022-01-27

申请号：US17209494

申请日：2021-03-23

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Tse-Yuan Lin ,  Chun-Ming Laio ,  Yu-Chih Cheng

IPC: H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  B32B17/10 ,  B32B7/14 ,  B32B27/36 ,  B32B27/20 ,  C08L67/02

Abstract: A carrier structure having a strengthening layer is provided. The strengthening layer comprises 5 to 30% by weight polysiloxane, 1 to 20% by weight silicon dioxide, and 60 to 85% by weight polyethylene terephthalate (PET) film. The carrier structure is used in a semiconductor packaging process for improving the process reliability.

公开(公告)号：US11545385B2

公开(公告)日：2023-01-03

申请号：US17209494

申请日：2021-03-23

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Tse-Yuan Lin ,  Chun-Ming Laio ,  Yu-Chih Cheng

IPC: H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  B32B17/10 ,  B32B7/14 ,  B32B27/36 ,  B32B27/20 ,  C08L67/02

Abstract: A carrier structure having a strengthening layer is provided. The strengthening layer comprises 5 to 30% by weight polysiloxane, 1 to 20% by weight silicon dioxide, and 60 to 85% by weight polyethylene terephthalate (PET) film. The carrier structure is used in a semiconductor packaging process for improving the process reliability.