公开(公告)号：US10354891B2

公开(公告)日：2019-07-16

申请号：US15945308

申请日：2018-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chih-Jen Yang ,  Yu-Chih Cheng ,  Chee-Key Chung ,  Chang-Fu Lin

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.

公开(公告)号：US20190181021A1

公开(公告)日：2019-06-13

申请号：US15945308

申请日：2018-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chih-Jen Yang ,  Yu-Chih Cheng ,  Chee-Key Chung ,  Chang-Fu Lin

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/568 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/06 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3512

Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.

公开(公告)号：US20160099204A1

公开(公告)日：2016-04-07

申请号：US14709510

申请日：2015-05-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chia-Cheng Chen ,  Chih-Jen Yang ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H05K1/11 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17106 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/18161 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/111 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads. Therefore, the conductive elements are prevented from being in contact with the conductive traces, and the problem that the conductive pads and the conductive traces are shorted is solved. The present invention further provides a method for fabricating the packaging substrate.

Abstract translation: 提供一种封装结构，包括：具有多个导电迹线的板; 多个导电焊盘，其形成在所述板上并且每个具有高于每个所述导电迹线的高度的高度; 以及电子部件，其经由多个导电元件设置在导电焊盘上并与其电连接，其中至少一个导电迹线位于至少一个导电焊盘附近。 因此，防止了导电元件与导电迹线接触，解决了导电焊盘和导电迹线短路的问题。 本发明还提供一种制造封装基板的方法。