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公开(公告)号：US09418931B2
公开(公告)日：2016-08-16
申请号：US14675761
申请日：2015-04-01
Applicant: Subtron Technology Co., Ltd.
Inventor： Chien-Ming Chen
IPC: H01L23/52 , H01L23/522 , H01L21/768 , H01L21/56 , H01L23/29
CPC classification number: H01L23/5226 , H01L21/486 , H01L21/56 , H01L21/568 , H01L21/76877 , H01L23/293 , H01L23/3121 , H01L23/3135 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/8203 , H05K1/185 , H05K3/4644 , H05K3/4697
Abstract: A manufacturing method of a package structure includes the following steps. A substrate including a core layer, first and second patterned metal layers is provided. The first and second patterned metal layers are respectively disposed on two opposite surfaces of the core layer. A through cavity penetrating the substrate is formed. The substrate is disposed on a tape carrier. A semiconductor component is disposed in the through cavity. An inner wall of the through cavity and a side surface of the semiconductor component define a groove. The filling compound is dispensed above the groove. A heating process is performed for the filling compound to flow toward the tape carrier and comprehensively fill the groove. First and second stacked layers are respectively laminated onto the first and second patterned metal layers and cover at least a part of the semiconductor component.
Abstract translation: 包装结构的制造方法包括以下步骤。 提供了包括芯层，第一和第二图案化金属层的衬底。 第一和第二图案化金属层分别设置在芯层的两个相对表面上。 形成穿透基板的通孔。 基板设置在带状载体上。 半导体部件设置在通孔中。 通孔的内壁和半导体部件的侧表面限定凹槽。 填充化合物被分配在凹槽上方。 进行加热处理以使填充化合物朝着带状载体流动，并且全面地填充凹槽。 第一和第二堆叠层分别层压到第一和第二图案化金属层上并覆盖半导体部件的至少一部分。
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Patent Agency Ranking
公开(公告)号：US09458540B2
公开(公告)日：2016-10-04
申请号：US14685610
申请日：2015-04-14
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Chien-Ming Chen
CPC classification number: B65D65/40 , B32B37/02 , B32B37/12 , B32B38/06 , B32B2038/047 , B32B2311/12 , B32B2457/08 , C25D5/022 , C25D5/12 , C25D7/00 , H01L25/0655 , H01L2224/0401 , H01L2224/04042 , H01L2224/11462 , H01L2924/15313
Abstract: A manufacturing method of a package substrate is provided. A first base is formed. Metal bumps are formed on the first base by plating. A second base having an upper and a lower surfaces, a core dielectric layer, a first and a second copper foil layers and containing cavities is provided. An adhesive layer is formed on inner walls of the containing cavities. The first and the second bases are laminated so that the metal bumps are disposed inside the containing cavities. A first base is removed. Blind via holes extending from the upper surface to the metal bumps are formed. A conductive material layer is formed on the first and the second copper foil layers, wherein the conductive material layer fills the blind via holes so as to define conductive through via holes. The conductive material layer is patterned to form a first and a second patterned metal layers.
Abstract translation: 提供封装基板的制造方法。 形成第一个基座。 通过电镀在第一基体上形成金属凸块。 提供具有上表面和下表面的第二基底，芯介质层，第一和第二铜箔层和容纳腔。 在容纳腔的内壁上形成粘合剂层。 层叠第一和第二基底，使得金属凸块设置在容纳腔内。 第一个基地被删除。 形成从上表面延伸到金属凸块的盲孔。 导电材料层形成在第一和第二铜箔层上，其中导电材料层填充盲孔，以便通过通孔限定导电。 图案化导电材料层以形成第一和第二图案化金属层。
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公开(公告)号：US09589942B2
公开(公告)日：2017-03-07
申请号：US14673883
申请日：2015-03-31
Applicant: Subtron Technology Co., Ltd.
Inventor： Chien-Ming Chen
IPC: H01L23/48 , H01L25/16 , H01L25/00 , H01L21/48 , H01L25/065 , H01L23/31 , H01L23/367 , H01L23/538 , H01L23/00 , H01L21/56
CPC classification number: H01L25/16 , H01L21/4803 , H01L21/4846 , H01L21/568 , H01L23/3121 , H01L23/3677 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16237 , H01L2225/06517 , H01L2225/06572 , H01L2225/06589 , H01L2924/19105 , H01L2924/19106
Abstract: A package structure includes a first substrate, a patterned solder mask, first thermal-conductive posts, a chip and a second substrate. The first substrate includes a first patterned metal layer, a second patterned metal layer, a first surface and a second surface. The first and second patterned metal layers are disposed on the first and second surfaces. The patterned solder mask disposed on the first and second patterned metal layers exposes part of the first and second patterned metal layers. The first thermal-conductive posts are disposed on the exposed first patterned metal layer and thermally coupled thereto. The chip is disposed on the first surface. The chip electrically connected to the first patterned metal layer is thermally coupled to the first thermal-conductive posts. Two opposite ends of each first thermal-conductive post are connected to the first and second substrates, and the first thermal-conductive posts are thermally coupled to the second substrate.
Abstract translation: 封装结构包括第一衬底，图案化焊接掩模，第一导热柱，芯片和第二衬底。 第一衬底包括第一图案化金属层，第二图案化金属层，第一表面和第二表面。 第一和第二图案化的金属层设置在第一和第二表面上。 布置在第一和第二图案化金属层上的图案化焊料掩模暴露第一和第二图案化金属层的一部分。 第一导热柱设置在暴露的第一图案化金属层上并与其热耦合。 芯片设置在第一表面上。 电连接到第一图案化金属层的芯片热耦合到第一导热柱。 每个第一导热柱的两个相对端连接到第一和第二基板，并且第一导热柱热耦合到第二基板。
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公开(公告)号：US20160230286A1
公开(公告)日：2016-08-11
申请号：US14685610
申请日：2015-04-14
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Chien-Ming Chen
CPC classification number: B65D65/40 , B32B37/02 , B32B37/12 , B32B38/06 , B32B2038/047 , B32B2311/12 , B32B2457/08 , C25D5/022 , C25D5/12 , C25D7/00 , H01L25/0655 , H01L2224/0401 , H01L2224/04042 , H01L2224/11462 , H01L2924/15313
Abstract: A manufacturing method of a package substrate is provided. A first base is formed. Metal bumps are formed on the first base by plating. A second base having an upper and a lower surfaces, a core dielectric layer, a first and a second copper foil layers and containing cavities is provided. An adhesive layer is formed on inner walls of the containing cavities. The first and the second bases are laminated so that the metal bumps are disposed inside the containing cavities. A first base is removed. Blind via holes extending from the upper surface to the metal bumps are formed. A conductive material layer is formed on the first and the second copper foil layers, wherein the conductive material layer fills the blind via holes so as to define conductive through via holes. The conductive material layer is patterned to form a first and a second patterned metal layers.
Abstract translation: 提供封装基板的制造方法。 形成第一个基座。 通过电镀在第一基体上形成金属凸块。 提供具有上表面和下表面的第二基底，芯介质层，第一和第二铜箔层和容纳腔。 在容纳腔的内壁上形成粘合剂层。 层叠第一和第二基底，使得金属凸块设置在容纳腔内。 第一个基地被删除。 形成从上表面延伸到金属凸块的盲孔。 导电材料层形成在第一和第二铜箔层上，其中导电材料层填充盲孔，以便通过通孔限定导电。 图案化导电材料层以形成第一和第二图案化金属层。
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公开(公告)号：US20160163614A1
公开(公告)日：2016-06-09
申请号：US14673883
申请日：2015-03-31
Applicant: Subtron Technology Co., Ltd.
Inventor： Chien-Ming Chen
CPC classification number: H01L25/16 , H01L21/4803 , H01L21/4846 , H01L21/568 , H01L23/3121 , H01L23/3677 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16237 , H01L2225/06517 , H01L2225/06572 , H01L2225/06589 , H01L2924/19105 , H01L2924/19106
Abstract: A package structure includes a first substrate, a patterned solder mask, first thermal-conductive posts, a chip and a second substrate. The first substrate includes a first patterned metal layer, a second patterned metal layer, a first surface and a second surface. The first and second patterned metal layers are disposed on the first and second surfaces. The patterned solder mask disposed on the first and second patterned metal layers exposes part of the first and second patterned metal layers. The first thermal-conductive posts are disposed on the exposed first patterned metal layer and thermally coupled thereto. The chip is disposed on the first surface. The chip electrically connected to the first patterned metal layer is thermally coupled to the first thermal-conductive posts. Two opposite ends of each first thermal-conductive post are connected to the first and second substrates, and the first thermal-conductive posts are thermally coupled to the second substrate.
Abstract translation: 封装结构包括第一衬底，图案化焊接掩模，第一导热柱，芯片和第二衬底。 第一衬底包括第一图案化金属层，第二图案化金属层，第一表面和第二表面。 第一和第二图案化的金属层设置在第一和第二表面上。 布置在第一和第二图案化金属层上的图案化焊料掩模暴露第一和第二图案化金属层的一部分。 第一导热柱设置在暴露的第一图案化金属层上并与其热耦合。 芯片设置在第一表面上。 电连接到第一图案化金属层的芯片热耦合到第一导热柱。 每个第一导热柱的两个相对端连接到第一和第二基板，并且第一导热柱热耦合到第二基板。
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公开(公告)号：US20160155702A1
公开(公告)日：2016-06-02
申请号：US14675761
申请日：2015-04-01
Applicant: Subtron Technology Co., Ltd.
Inventor： Chien-Ming Chen
IPC: H01L23/522 , H01L21/56 , H01L23/29 , H01L21/768
CPC classification number: H01L23/5226 , H01L21/486 , H01L21/56 , H01L21/568 , H01L21/76877 , H01L23/293 , H01L23/3121 , H01L23/3135 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/8203 , H05K1/185 , H05K3/4644 , H05K3/4697
Abstract: A manufacturing method of a package structure includes the following steps. A substrate including a core layer, first and second patterned metal layers is provided. The first and second patterned metal layers are respectively disposed on two opposite surfaces of the core layer. A through cavity penetrating the substrate is formed. The substrate is disposed on a tape carrier. A semiconductor component is disposed in the through cavity. An inner wall of the through cavity and a side surface of the semiconductor component define a groove. The filling compound is dispensed above the groove. A heating process is performed for the filling compound to flow toward the tape carrier and comprehensively fill the groove. First and second stacked layers are respectively laminated onto the first and second patterned metal layers and cover at least a part of the semiconductor component.
Abstract translation: 包装结构的制造方法包括以下步骤。 提供了包括芯层，第一和第二图案化金属层的衬底。 第一和第二图案化金属层分别设置在芯层的两个相对表面上。 形成穿透基板的通孔。 基板设置在带状载体上。 半导体部件设置在通孔中。 通孔的内壁和半导体部件的侧表面限定凹槽。 填充化合物被分配在凹槽上方。 进行加热处理以使填充化合物朝着带状载体流动，并且全面地填充凹槽。 第一和第二堆叠层分别层压到第一和第二图案化金属层上并覆盖半导体部件的至少一部分。
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