公开(公告)号：US20170251552A1

公开(公告)日：2017-08-31

申请号：US15594673

申请日：2017-05-15

Applicant: Subtron Technology Co., Ltd.

Inventor： Chih-Hong Chuang ,  Chien-Hung Wu

IPC: H05K1/09 ,  H05K3/46 ,  H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H01L21/683

CPC classification number: H05K1/09 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2221/68381 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/007 ,  H05K3/18 ,  H05K3/205 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/4638 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2203/03

Abstract: A temporary package substrate includes a first copper layer, a second copper layer, a third copper layer, a first plating copper layer, a second plating copper layer, a third plating copper layer, a first dielectric layer, a second dielectric layer and two circuit structures. The second copper layer is located between the first and the third copper layers, and edges of the second copper layer are retracted a distance compared to edges of the first copper layer and edges of the third copper layer. The first and the second dielectric layers completely encapsulate the edges of the second copper layer and the edges of the second plating copper layer. Each of the circuit structures includes at least two patterned circuit layers, an insulation layer located between the patterned circuit layers, and a plurality of conductive through hole structures penetrating the insulation layer and electrically connected with the patterned circuit layers.

公开(公告)号：US10123413B2

公开(公告)日：2018-11-06

申请号：US15594673

申请日：2017-05-15

Applicant: Subtron Technology Co., Ltd.

Inventor： Chih-Hong Chuang ,  Chien-Hung Wu

IPC: H05K3/00 ,  H01K1/00 ,  H05K1/09 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H05K3/46 ,  H05K1/02 ,  H05K1/11 ,  H05K3/18 ,  H05K3/40 ,  H05K3/20 ,  H05K3/42

Abstract: A temporary package substrate includes a first copper layer, a second copper layer, a third copper layer, a first plating copper layer, a second plating copper layer, a third plating copper layer, a first dielectric layer, a second dielectric layer and two circuit structures. The second copper layer is located between the first and the third copper layers, and edges of the second copper layer are retracted a distance compared to edges of the first copper layer and edges of the third copper layer. The first and the second dielectric layers completely encapsulate the edges of the second copper layer and the edges of the second plating copper layer. Each of the circuit structures includes at least two patterned circuit layers, an insulation layer located between the patterned circuit layers, and a plurality of conductive through hole structures penetrating the insulation layer and electrically connected with the patterned circuit layers.

公开(公告)号：US09693468B2

公开(公告)日：2017-06-27

申请号：US14846991

申请日：2015-09-07

Applicant: Subtron Technology Co., Ltd.

Inventor： Chih-Hong Chuang ,  Chien-Hung Wu

IPC: H05K3/00 ,  H05K3/40 ,  H01K1/00 ,  H05K3/46 ,  H01L21/48 ,  H01L21/683 ,  H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K3/18 ,  H01L23/498

CPC classification number: H05K1/09 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2221/68381 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/007 ,  H05K3/18 ,  H05K3/205 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/4638 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2203/03

Abstract: A method of manufacturing a package substrate is provided. A first copper layer and a first plating copper layer formed thereon, a first dielectric layer, a second copper layer and a second plating copper layer formed thereon, a second dielectric layer, a third copper layer and a third plating copper layer formed thereon are provided and laminated, so that the first and the second dielectric layers encapsulate edges of the second copper layer and the second plating copper layer to form a temporary carrier. Two circuit structures are formed on two opposite surfaces of the temporary carrier. The temporary carrier and the circuit structures are cut to expose the edges of the second copper layer and the second plating copper layer, and separated along the exposed edges of the second copper layer and the second plating copper layer to form two package substrates independent from each other.

公开(公告)号：US20170006713A1

公开(公告)日：2017-01-05

申请号：US14846991

申请日：2015-09-07

Applicant: Subtron Technology Co., Ltd.

Inventor： Chih-Hong Chuang ,  Chien-Hung Wu

IPC: H05K3/46 ,  H05K1/11 ,  H05K1/09 ,  H05K1/02 ,  H05K3/18 ,  H05K3/40

CPC classification number: H05K1/09 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2221/68381 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/007 ,  H05K3/18 ,  H05K3/205 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/4638 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2203/03

Abstract: A method of manufacturing a package substrate is provided. A first copper layer and a first plating copper layer formed thereon, a first dielectric layer, a second copper layer and a second plating copper layer formed thereon, a second dielectric layer, a third copper layer and a third plating copper layer formed thereon are provided and laminated, so that the first and the second dielectric layers encapsulate edges of the second copper layer and the second plating copper layer to form a temporary carrier. Two circuit structures are formed on two opposite surfaces of the temporary carrier. The temporary carrier and the circuit structures are cut to expose the edges of the second copper layer and the second plating copper layer, and separated along the exposed edges of the second copper layer and the second plating copper layer to form two package substrates independent from each other.

Abstract translation: 提供一种制造封装基板的方法。 提供了形成在其上的第一铜层和第一电镀铜层，形成在其上的第一电介质层，第二铜层和第二电镀铜层，形成在其上的第二电介质层，第三铜层和第三电镀铜层 并且层叠，使得第一和第二电介质层封装第二铜层和第二电镀铜层的边缘以形成临时载体。 在临时载体的两个相对的表面上形成两个电路结构。 切割临时载体和电路结构以暴露第二铜层和第二镀铜层的边缘，并沿着第二铜层和第二镀铜层的暴露边缘分离以形成独立于每个的两个封装衬底 其他。