公开(公告)号：US20180102330A1

公开(公告)日：2018-04-12

申请号：US15291111

申请日：2016-10-12

Applicant: SunASIC Technologies, Inc.

Inventor： Chung-Hao HSIEH ,  Chi-Chou LIN ,  Zheng-Ping HE

IPC: H01L23/60 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A chip package having ESD protection and a method for making the chip are disclosed. The chip package includes a chip and a substrate. The chip includes a number of I/O pads each connected to a corresponding I/O contact via a first bonding wire. It also includes a number of ESD protective pads each connected to a corresponding ESD contact via a second bonding wire. Bonding wires connecting the ESD protective pads and the ESD contacts have vertexes closer to the top surface of the chip than the vertexes of the bonding wires connecting the I/O pads and the I/O contacts. Hence, a perfect ESD protection effect is achieved by leading the ESD through the bonding wires to the ESD contacts rather than via the I/O contacts.