公开(公告)号：US20210257326A1

公开(公告)日：2021-08-19

申请号：US17307938

申请日：2021-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： JING-CHENG LIN ,  FENG-CHENG HSU

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/66

Abstract: A method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a plurality of conductive bumps on the plurality of pads correspondingly; disposing a solder bracing material surrounding the plurality of conductive bumps and over the surface of the substrate after the disposing of the plurality of conductive bumps, wherein the solder bracing material is in contact with a sidewall of each of the plurality of pads and the plurality of conductive bumps; disposing a release film on the solder bracing material and the plurality of conductive bumps; and removing the release film to form a rough surface of the solder bracing material. The rough surface of the solder bracing material includes a plurality of protruded portions and a plurality of recessed portions.

公开(公告)号：US20180082954A1

公开(公告)日：2018-03-22

申请号：US15811067

申请日：2017-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： JING-CHENG LIN ,  PO-HAO TSAI ,  YING CHING SHIH ,  SZU WEI LU

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L21/683 ,  H01L25/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83385 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01028 ,  H01L2924/01023 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die.

公开(公告)号：US20150008587A1

公开(公告)日：2015-01-08

申请号：US13935167

申请日：2013-07-03

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： JING-CHENG LIN ,  JUI-PIN HUNG ,  PO-HAO TSAI

IPC: H01L23/373 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/528 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A fan-out package includes a molding compound, a conductive plug and a stress buffer. The conductive plug is in the molding compound. The stress buffer is between the conductive plug and the molding compound. The stress buffer has a coefficient of thermal expansion (CTE). The CTE of the stress buffer is between a CTE of the molding compound and a CTE of the conductive plug. A method of manufacturing a three dimensional includes plating a post on a substrate, and disposing a stress buffer on the sidewall of the post. The method further includes surrounding the stress buffer with a molding compound.

Abstract translation: 扇出包装包括模塑料，导电塞和应力缓冲。 导电塞在模塑料中。 应力缓冲液位于导电塞和模塑料之间。 应力缓冲器具有热膨胀系数（CTE）。 应力缓冲器的CTE在模塑料的CTE和导电塞的CTE之间。 制造三维的方法包括在基板上电镀柱，并将应力缓冲层设置在柱的侧壁上。 该方法还包括用模塑料包围应力缓冲液。

公开(公告)号：US20190279966A1

公开(公告)日：2019-09-12

申请号：US16410753

申请日：2019-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： JING-CHENG LIN ,  YING-CHING SHIH ,  PU WANG ,  CHEN-HUA YU

IPC: H01L25/065 ,  H01L21/683 ,  H01L23/31 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10

Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

公开(公告)号：US20190035738A1

公开(公告)日：2019-01-31

申请号：US16146968

申请日：2018-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： JING-CHENG LIN ,  PO-HAO TSAI ,  YING CHING SHIH ,  SZU WEI LU

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L21/683 ,  H01L25/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

Abstract: The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die.

公开(公告)号：US20170141079A1

公开(公告)日：2017-05-18

申请号：US14939253

申请日：2015-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHIN-FU KAO ,  TSEI-CHUNG FU ,  JING-CHENG LIN

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/08145 ,  H01L2224/1161 ,  H01L2224/11616 ,  H01L2224/11831 ,  H01L2224/13009 ,  H01L2224/13019 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/1601 ,  H01L2224/16012 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73201 ,  H01L2224/73204 ,  H01L2224/80075 ,  H01L2224/80203 ,  H01L2224/80896 ,  H01L2224/8101 ,  H01L2224/81011 ,  H01L2224/81012 ,  H01L2224/81022 ,  H01L2224/81075 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/83075 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/1434 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/01014 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/01029 ,  H01L2924/00

Abstract: The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least partially protruding from the first joining surface, a second device having a second joining surface facing the first joining surface, and a second conductive component at least exposing from the second joining surface. The first conductive component and the second conductive component form a joint having a first beak. The first beak points to either the first joining surface or the second joining surface.

公开(公告)号：US20240379429A1

公开(公告)日：2024-11-14

申请号：US18780552

申请日：2024-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： JING-CHENG LIN ,  YING-CHING SHIH ,  PU WANG ,  CHEN-HUA YU

IPC: H01L21/768 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The method includes: forming a carrier; forming a sacrificial layer on the carrier; forming a through via on the sacrificial layer, wherein the through via includes a seed layer and a metal feature; disposing a die on the sacrificial layer, wherein the die has a plurality of metal pillars disposed at a side of the die facing away from the sacrificial layer; forming a molding compound on the sacrificial layer to cover and surround the die and the through via; removing a portion of the molding compound and a portion of the through via above the die to expose the metal feature of the through via; and removing the carrier and sacrificial layer to expose the seed layer of the through via.

公开(公告)号：US20200152610A1

公开(公告)日：2020-05-14

申请号：US16742285

申请日：2020-01-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： JING-CHENG LIN ,  YING-CHING SHIH ,  PU WANG ,  CHEN-HUA YU

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L21/768 ,  H01L21/683 ,  H01L21/56 ,  H01L25/10

Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

公开(公告)号：US20190096868A1

公开(公告)日：2019-03-28

申请号：US15718837

申请日：2017-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HSIEN-JU TSOU ,  CHIH-WEI WU ,  PU WANG ,  YING-CHING SHIH ,  SZU-WEI LU ,  JING-CHENG LIN

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/373 ,  H01L23/29 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.

公开(公告)号：US20180269124A1

公开(公告)日：2018-09-20

申请号：US15982332

申请日：2018-05-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： NAI-WEI LIU ,  JUI-PIN HUNG ,  JING-CHENG LIN

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/311 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor device includes a die having a pad, a passivation disposed aver the die and a portion of the pad, a polymer disposed over the passivation, a molding surrounding the die and the polymer, and an interface between the polymer and the molding. The interface and the passivation define an angle less than or greater than approximately 90°.