公开(公告)号：US3789239A

公开(公告)日：1974-01-29

申请号：US3789239D

申请日：1971-07-12

Applicant: TELETYPE CORP

Inventor： HEEREN R

IPC: G11C19/18 ,  H03K19/096 ,  G11C11/40

CPC classification number: H03K19/096 ,  G11C19/184

Abstract: A MOSFET shift register wherein capacitor nodes in each cell of the register are charged and selectively discharged and having booster capacitor nodes and clock nodes to increase slightly the voltages at the capacitor nodes in order to enhance the operation of the shift register.

Abstract translation: MOSFET移位寄存器，其中寄存器的每个单元中的电容器节点被充电并选择性地放电，并且具有升压电容器节点和时钟节点以稍微增加电容器节点处的电压，以便增强移位寄存器的操作。

公开(公告)号：US3838404A

公开(公告)日：1974-09-24

申请号：US36137773

申请日：1973-05-17

Applicant: TELETYPE CORP

Inventor： HEEREN R

IPC: G11C11/419 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4097 ,  H03K5/02 ,  G11C13/00

CPC classification number: G11C11/4097 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4091 ,  H03K5/023

Abstract: In an array of memory cells having the cells in each column coupled together by one of a plurality of address buses, the ground reference potential for each cell is provided by coupling a storage capacitor in each cell to an adjacent address bus. Since only one address bus is addressed at any selected time, the adjacent address buses remain at ground potential so that coupling of the storage capacitors in each addressed cell to the adjacent, grounded address buses supplies the required reference ground for each addressed cell. Refreshing, or restoring of the charges on the storage capacitor in each memory cell is accomplished by a plurality of sense-refresh amplifiers. Each sense-refresh amplifier can be coupled to a selected cell capacitor in a row of memory cells, and includes a first pair of MOSFET devices cross-coupled in a flip-flop configuration. In one embodiment, single phase clock signals are applied to the first pair of MOSFET''s through an ON biased second pair of MOSFET''s. The clock signals thus applied synchronize the read, write, and refresh functions of the memory. Alternatively, single phase clock signals can be applied to a third pair of MOSFET''s coupled in parallel with the first pair, or a clock pulse can be used to short a pair of circuit nodes during an initial time period to bring a pair of load capacitances to a desired, low initial potential. Data signals are applied to and read-out from only one side of the sense-refresh amplifier, and the sense-refresh amplifier also serves to invert the data stored in memory cells on the opposite side, and to re-invert the data on read out.

Abstract translation: 在具有通过多个地址总线之一耦合在一起的各列中的单元的存储单元的阵列中，通过将每个单元中的存储电容器耦合到相邻的地址总线来提供每个单元的接地参考电位。 由于在任何选定的时间仅寻址一个地址总线，所以相邻的地址总线保持接地电位，使得每个寻址的单元中的存储电容器与相邻的接地地址总线的耦合为每个寻址的单元提供所需的参考地。 通过多个感测刷新放大器来实现每个存储单元中的存储电容器上的电荷的刷新或恢复。 每个感测刷新放大器可以耦合到一行存储器单元中的所选单元电容器，并且包括以触发器配置交叉耦合的第一对MOSFET器件。 在一个实施例中，通过ON偏置的第二对MOSFET将单相时钟信号施加到第一对MOSFET。 这样应用的时钟信号同步存储器的读，写和刷新功能。 或者，单相时钟信号可以被施加到与第一对并联耦合的第三对MOSFET，或者可以使用时钟脉冲来在初始时间段期间缩短一对电路节点以使一对负载电容 期望的低初始电位。 数据信号仅从感测刷新放大器的一侧施加到读出，并且感测刷新放大器还用于反转存储在相对侧的存储单元中的数据，并重新反转读取的数据 出来