公开(公告)号：US10062661B2

公开(公告)日：2018-08-28

申请号：US15628851

申请日：2017-06-21

Applicant: Tessera, Inc.

Inventor： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L27/146 ,  H01L25/04 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L24/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L24/73 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L27/14618 ,  H01L27/14625 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1713 ,  H01L2224/17179 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48464 ,  H01L2224/49105 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01049 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/00

Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

公开(公告)号：US09716075B2

公开(公告)日：2017-07-25

申请号：US14851925

申请日：2015-09-11

Applicant: Tessera, Inc.

Inventor： Teck-Gyu Kang ,  Wei-Shun Wang ,  Hiroaki Sato ,  Kiyoaki Hashimoto ,  Yoshikuni Nakadaira ,  Norihito Masuda ,  Belgacem Haba ,  Ilyas Mohammed ,  Philip Damberg

IPC: B23K31/02 ,  H01L23/00 ,  B23K1/00 ,  H05K1/11 ,  H05K3/40 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H05K3/34 ,  H01L23/31

CPC classification number: H01L24/81 ,  B23K1/0016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8138 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/831 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/341 ,  H05K3/4007 ,  H05K2201/0195 ,  Y10T29/49126 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

公开(公告)号：US20160005711A1

公开(公告)日：2016-01-07

申请号：US14851925

申请日：2015-09-11

Applicant: Tessera, Inc.

Inventor： Teck-Gyu Kang ,  Wei-Shun Wang ,  Hiroaki Sato ,  Kiyoaki Hashimoto ,  Yoshikuni Nakadaira ,  Norihito Masuda ,  Belgacem Haba ,  Ilyas Mohammed ,  Philip Damberg

IPC: H01L23/00 ,  H01L21/48 ,  H05K3/34 ,  H01L21/56

CPC classification number: H01L24/81 ,  B23K1/0016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8138 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/831 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/341 ,  H05K3/4007 ,  H05K2201/0195 ,  Y10T29/49126 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Abstract translation: 微电子组件可以包括包括具有导电元件的刚性介电层的基板，具有在其表面暴露的多个触点的微电子元件以及延伸穿过刚性介电层上的柔性介电层的导电通孔。 通孔将基板触点分别电连接到导电元件，并且基板触点分别连接到微电子元件的触点。 通孔，柔性层和衬底触点适于明显地减轻与组件的差分热接触和膨胀相关联的衬底触点处的应力。

公开(公告)号：US09224717B2

公开(公告)日：2015-12-29

申请号：US14564640

申请日：2014-12-09

Applicant: Tessera, Inc.

Inventor： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

IPC: H01L25/04 ,  H01L23/13 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L27/146 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L24/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L24/73 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L27/14618 ,  H01L27/14625 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1713 ,  H01L2224/17179 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48464 ,  H01L2224/49105 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01049 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

公开(公告)号：US20140145329A1

公开(公告)日：2014-05-29

申请号：US14168386

申请日：2014-01-30

Applicant: TESSERA, INC.

Inventor： Belgacem Haba ,  Yoichi Kubota ,  Teck-Gyu Kang ,  Jae M. Park

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/4828 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K3/061 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0369 ,  H05K2203/0597 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T428/24174 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method includes applying a final etch-resistant material to an in-process substrate so that the final etch-resistant material at least partially covers first microcontact portions integral with the substrate and projecting upwardly from a surface of the substrate, and etching the surface of the substrate so as to leave second microcontact portions below the first microcontact portions and integral therewith, the final etch-resistant material at least partially protecting the first microcontact portions from etching during the further etching step. A microelectronic unit includes a substrate, and a plurality of microcontacts projecting in a vertical direction from the substrate, each microcontact including a base region adjacent the substrate and a tip region remote from the substrate, each microcontact having a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Abstract translation: 一种方法包括将最终的耐蚀刻材料施加到工艺衬底，使得最终耐蚀刻材料至少部分地覆盖与衬底成一体的第一微接触部分并从衬底的表面向上突出，并且蚀刻表面 衬底，以便将第二微接触部分留在第一微接触部分下方并与之成一体，最后的抗蚀刻材料在另外的蚀刻步骤期间至少部分地保护第一微接触部分免受蚀刻。 微电子单元包括衬底以及从衬底沿垂直方向突出的多个微接点，每个微接触器包括邻近衬底的基极区域和远离衬底的尖端区域，每个微接触体具有作为第一功能的水平尺寸 在基部区域中垂直位置，并且其是尖端区域中垂直位置的第二函数。

公开(公告)号：US09984901B2

公开(公告)日：2018-05-29

申请号：US14933225

申请日：2015-11-05

Applicant: Tessera, Inc.

Inventor： Belgacem Haba ,  Teck-Gyu Kang ,  Ilyas Mohammed ,  Ellis Chau

IPC: H01L21/00 ,  H01L21/56 ,  G01R31/28 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L21/565 ,  G01R31/2886 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials.

公开(公告)号：US20140213021A1

公开(公告)日：2014-07-31

申请号：US14242279

申请日：2014-04-01

Applicant: TESSERA, INC.

Inventor： Belgacem Haba ,  Teck-Gyu Kang ,  Ilyas Mohammed ,  Ellis Chau

IPC: H01L21/56

CPC classification number: H01L21/565 ,  G01R31/2886 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials.

Abstract translation: 制造微电子组件的方法可以包括将电介质材料模制成围绕安装有微电子元件的衬底的高度突出的至少两个导电元件，使得导电元件的远端表面保持可接近并暴露在从 模制电介质材料的外表面。 所述远程表面可以从所述衬底的所述表面高度设置，所述表面低于或高于所述模制电介质材料的外表面与所述衬底表面的高度。 导电元件可被布置成同时携带第一和第二不同的电势：例如功率，接地或信号电位。

公开(公告)号：US20130203216A1

公开(公告)日：2013-08-08

申请号：US13792521

申请日：2013-03-11

Applicant: Tessera, Inc.

Inventor： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

IPC: H01L21/48

CPC classification number: H01L21/4885 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49517 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

公开(公告)号：US20210050322A1

公开(公告)日：2021-02-18

申请号：US17086785

申请日：2020-11-02

Applicant: Tessera, Inc.

Inventor： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L25/04 ,  H01L27/146

Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

公开(公告)号：US10593643B2

公开(公告)日：2020-03-17

申请号：US16058425

申请日：2018-08-08

Applicant: Tessera, Inc.

Inventor： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L25/04 ,  H01L27/146 ,  H01L21/56 ,  H01L23/538

Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.