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公开(公告)号：US20250004492A1
公开(公告)日：2025-01-02
申请号：US18217388
申请日：2023-06-30
Applicant: Texas Instruments Incorporated
Inventor： Harikrishna Parthasarathy , Khyati Bansal , Venkatesh Kadlimatti , Kunal Karanjkar
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed corresponding to a voltage regulator. An example circuit includes an output terminal; a first transistor including a current terminal and a control terminal coupled to an output terminal; a second transistor including a control terminal and a current terminal coupled to the control terminal of the first transistor; a third transistor including a first current terminal and a second current terminal, the first current terminal of the third transistor coupled to the output terminal; current mirror circuitry including a terminal coupled to the second current terminal of the third transistor; and inverter circuitry including an input terminal and an output terminal, the input terminal coupled to the terminal of the current mirror and the second current terminal of the third transistor, the output terminal coupled to the control terminal of the second transistor.
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Patent Agency Ranking
公开(公告)号：US20230152828A1
公开(公告)日：2023-05-18
申请号：US18089433
申请日：2022-12-27
Applicant: Texas Instruments Incorporated
Inventor： Rinu Mathew , Harikrishna P , Venkatesh Kadlimatti
CPC classification number: G05F1/56 , H03F3/45475
Abstract: In described examples, a low dropout voltage regulator includes an input voltage terminal, a resistive element, first and second transistors, an output terminal, a differential amplifier, and first and second saturation prevention circuits. The resistive element is coupled between the input voltage terminal and a gate of the first transistor. The output terminal is coupled to the drain of the first transistor and the source of the second transistor. A first input of the differential amplifier receives a reference voltage, and a second input is coupled to the output terminal. The first saturation prevention circuit provides a first clamp current to the differential amplifier output if the gate-source voltage of the first transistor is less than a first threshold voltage. The second saturation prevention circuit provides a second clamp current to the differential amplifier output if the gate-source voltage of the second transistor is greater than a second threshold voltage.
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公开(公告)号：US20250103077A1
公开(公告)日：2025-03-27
申请号：US18371537
申请日：2023-09-22
Applicant: Texas Instruments Incorporated
Inventor： Rinu Mathew , Venkatesh Kadlimatti , Harikrishna Parthasarathy
Abstract: A power supply system may include multiple DC-to-DC (direct current) voltage regulators coupled in parallel to a load, and control circuitry to control the parallel-operating regulators. The control circuitry may include a first share control circuit, a second share control circuit, and a voltage regulation circuit. The first and second share control circuits may operate together with the voltage regulation circuit to control, respectively, the parallel-operating regulators to regulate a common output voltage. Additionally, first and second share control circuits may operate together with the voltage regulation circuit to control respective share of the load current by the parallel-operating regulators.
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4.发明授权公开(公告)号：US12181902B2
公开(公告)日：2024-12-31
申请号：US17683217
申请日：2022-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rinu Mathew , Vineet Khurana , Anand Kumar G , Aniruddha Periyapatna Nagendra , Venkatesh Kadlimatti , Torjus Lyng Kallerud
Abstract: In an example, a device includes a controller and a direct current (DC)-to-DC converter coupled to the controller and configured to provide a load current to a load. The device also includes a low-dropout (LDO) regulator coupled to the DC-to-DC converter. The controller includes digital logic, and the digital logic is configured to determine the load current. The digital logic is configured to turn on the LDO regulator if the load current is above a predetermined threshold. The digital logic is also configured to turn off the LDO regulator if the load current is below the predetermined threshold.
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公开(公告)号：US20250141462A1
公开(公告)日：2025-05-01
申请号：US18498672
申请日：2023-10-31
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Kadlimatti , Rinu Mathew
Abstract: In described examples, an integrated circuit (IC) includes multiple subcircuits. The subcircuits include a first subcircuit that receives a current and sinks a portion of the current that is responsive to a threshold. In response to the current being greater than the threshold, the first subcircuit provides a difference between the current and the portion to a second subcircuit and asserts a signal corresponding to an ordinality of the first subcircuit. The second subcircuit is configured to repeat the actions with respect to the first subcircuit, with the second subcircuit in place of the first subcircuit and a third subcircuit in place of the second subcircuit, and with the difference in place of the current, in response to the IC comprising the third subcircuit.
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公开(公告)号：US20240361794A1
公开(公告)日：2024-10-31
申请号：US18309340
申请日：2023-04-28
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Kadlimatti , Aritra Chowdhury , Harikrishna P
Abstract: In described examples, a voltage glitch detector includes a current source, a latch, and first, second, third, fourth, and fifth transistors. A source of the third transistor is coupled to a source of the second transistor, and a gate and drain of the third transistor is coupled to gates of the first and second transistors and a first terminal of the current source. A drain of the fourth transistor is coupled to a drain of the first transistor and an input of the latch. A source of the fifth transistor is coupled to a source of the fourth transistor and the second terminal of the current source. A gate and drain of the fifth transistor is coupled to a gate of the fourth transistor and a drain of the second transistor.
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