公开(公告)号：US20180061892A1

公开(公告)日：2018-03-01

申请号：US15790535

申请日：2017-10-23

Applicant: TOPPAN PRINTING CO., LTD.

Inventor： Hina CHUJO ,  Mamoru Ishizaki

IPC: H01L27/28 ,  H01L51/05 ,  H01L51/10 ,  H01L51/00

CPC classification number: H01L27/283 ,  H01L27/1292 ,  H01L27/3274 ,  H01L29/786 ,  H01L51/0005 ,  H01L51/0022 ,  H01L51/0545 ,  H01L51/105 ,  H01L51/107

Abstract: A thin film transistor array formed substrate including a gate electrode, a gate insulation layer, a source wiring structure including a source wiring and a source electrode, a drain electrode, a pixel electrode connected to the drain electrode, a semiconductor layer formed in a stripe shape having a longitudinal side extending in a direction that the source wiring extends, and a protection layer formed to cover an entire portion of the semiconductor layer. The source wiring structure has notch portions positioned in the direction that the source wiring extends such that the notch portions overlap with the gate electrode, the source wiring has a first portion having a first width where the notch portions are formed and a second portion having a second width larger than the first width where no notch portions are formed, and the source wiring has an opening in the second portion.