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公开(公告)号：US20200091235A1
公开(公告)日：2020-03-19
申请号：US16290651
申请日：2019-03-01
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Kazuhiko YAMAMOTO
Abstract: A storage device includes: a first conductive layer; a second conductive layer; and a resistance-variable layer disposed between the first conductive layer and the second conductive layer, and including a first chalcogenide containing a first element which is either silicon or germanium. An insulating layer is disposed in a second direction perpendicular to a first direction from the first conductive layer to the second conductive layer with respect to the resistance-variable layer. A first region is disposed between the resistance-variable layer and the insulating layer, and has a third concentration of the first element higher than both a first concentration of the first element in the resistance-variable layer and a second concentration of the first element in the insulating layer.
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公开(公告)号：US20190287979A1
公开(公告)日：2019-09-19
申请号：US16122541
申请日：2018-09-05
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Kana HIRAYAMA , Kazuhiko YAMAMOTO , Kunifumi SUZUKI
Abstract: A nonvolatile semiconductor memory device includes a first wiring layer, multiple second wiring layers provided above the first wiring layer and arrayed along a direction perpendicular to a semiconductor substrate, a semiconductor layer extending along the direct ion and electrically connected to the first wiring layer, a first insulating layer extending along the direction and provided between the semiconductor layer and the multiple second wiring layers, a first oxide layer extending along the direction and provided between the first insulating layer and the multiple second wiring layers, and multiple second oxide layers having first sides being respectively in contact with the multiple second wiring layers and having second sides being in contact with the first oxide layer, a resistance value of a stacked film configured with the first oxide layer and the multiple second oxide layers varying according to a voltage being applied to the multiple second wiring layers.
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公开(公告)号：US20190296079A1
公开(公告)日：2019-09-26
申请号：US16129249
申请日：2018-09-12
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Yosuke MURAKAMI , Yusuke ARAYASHIKI , Kazuhiko YAMAMOTO
IPC: H01L27/24
Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a first signal line, a first conductive layer, a first storage layer and a first insulation layer. The first signal line extends in a first direction crossing the substrate. The first conductive layer extends in a second direction crossing the first direction and being parallel to the substrate, and has a first surface and a second surface that is away from the first signal line in a third direction crossing the first and second directions. The first storage layer is provided between the first signal line and the first conductive layer. The first insulation layer is provided between the second surface and the first storage layer.
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公开(公告)号：US20190156888A1
公开(公告)日：2019-05-23
申请号：US16252629
申请日：2019-01-19
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Kunifumi SUZUKI , Kazuhiko YAMAMOTO
IPC: G11C13/00
Abstract: According to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to perform transition of a resistive state of the memory cell. The control circuit performs a first writing operation by applying a first pulse having a voltage of a first polarity to the memory cell and applying a second pulse having a voltage of the first polarity smaller than the voltage of the first pulse to the memory cell continuously after applying the first pulse.
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公开(公告)号：US20190074438A1
公开(公告)日：2019-03-07
申请号：US15916805
申请日：2018-03-09
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Kazuhiko YAMAMOTO , Kunifumi SUZUKI , Tomotaka ARIGA
IPC: H01L45/00
Abstract: A memory device includes a crystal-including layer including a first metal, and a germanium-and-oxygen including layer contacting the crystal-including layer. At least a portion of the crystal-including layer is crystallized. The germanium-and-oxygen including layer includes germanium and oxygen.
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Patent Agency Ranking
公开(公告)号：US20200083295A1
公开(公告)日：2020-03-12
申请号：US16279971
申请日：2019-02-19
Applicant: Toshiba Memory Corporation
Inventor： Yosuke MURAKAMI , Takeshi ISHIZAKI , Yusuke ARAYASHIKI , Kazuhiko YAMAMOTO , Kana HIRAYAMA
Abstract: A storage device includes a first conductor, a resistance variable film, and a second conductor. The resistance variable film includes a first layer and a second layer. The second layer is located on a side opposite to the first conductor with respect to the first layer, contains oxygen, and has conductivity higher than that of the first layer. The second conductor includes a first portion and a second portion. The first portion abuts on the second layer of the resistance variable film. The second portion is separated from the resistance variable film as compared to the first portion. The oxygen content of the first portion is higher than that of the second portion.
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公开(公告)号：US20190088716A1
公开(公告)日：2019-03-21
申请号：US15910690
申请日：2018-03-02
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Kunifumi SUZUKI , Kazuhiko YAMAMOTO
CPC classification number: H01L27/249 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C13/0097 , G11C2013/0078 , G11C2013/009 , G11C2213/32 , G11C2213/51 , G11C2213/71 , G11C2213/77 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/1641
Abstract: A memory device is described. A first conductive layer extends in a first direction. A second conductive layer extends in the first direction. A third conductive layer extends in a second direction intersecting the first direction. A first oxide region is disposed between the first conductive layer and the third conductive layer and between the second conductive layer and the third conductive layer. A semiconductor region is disposed between the first conductive layer and the first oxide region and between the first conductive layer and the second conductive layer. A second distance between the semiconductor region, which is disposed between the first conductive layer and the second conductive layer, and the third conductive layer, is longer than a first distance between the semiconductor region, which is disposed between the first conductive layer and the first oxide region, and the third conductive layer.
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公开(公告)号：US20180261651A1
公开(公告)日：2018-09-13
申请号：US15697388
申请日：2017-09-06
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Kana HIRAYAMA , Kazuhiko YAMAMOTO , Yusuke ARAYASHIKI , Yosuke MURAKAMI , Yusuke KOBAYASHI
CPC classification number: H01L27/249 , G11C13/0007 , G11C13/0069 , G11C13/0097 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/71 , H01L27/2436 , H01L45/08 , H01L45/1226 , H01L45/1246 , H01L45/1253 , H01L45/146
Abstract: According to one or more embodiments, a memory device includes a first interconnection extending in a first direction, a plurality of second interconnections extending in a second direction intersecting the first direction, and a first resistance change film provided between the first interconnection and the second interconnections. The first resistance change film includes a first conductive layer having a first conductivity, and a second conductive layer provided between the first conductive layer and the plurality of second interconnections and having a second conductivity higher than the first conductivity.
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公开(公告)号：US20180130529A1
公开(公告)日：2018-05-10
申请号：US15830311
申请日：2017-12-04
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Kunifumi SUZUKI , Kazuhiko YAMAMOTO
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C2013/0092 , G11C2213/11 , G11C2213/33 , G11C2213/34 , G11C2213/77
Abstract: According to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to perform transition of a resistive state of the memory cell. The control circuit performs a first writing operation by applying a first pulse having a voltage of a first polarity to the memory cell and applying a second pulse having a voltage of the first polarity smaller than the voltage of the first pulse to the memory cell continuously after applying the first pulse.
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公开(公告)号：US20200091171A1
公开(公告)日：2020-03-19
申请号：US16267878
申请日：2019-02-05
Applicant: Toshiba Memory Corporation
Inventor： Hiroki TOKUHIRA , Kazuhiko YAMAMOTO , Kunifumi SUZUKI
IPC: H01L27/11582 , H01L29/51
Abstract: A semiconductor memory device includes a stacked body including insulating layers and gate electrode layers alternately stacked in a direction, a semiconductor layer extending in the direction, and a gate insulating layer provided between the semiconductor layer and the gate electrode layer, and including a first layer, a second layer, and a third layer between the first layer and the second layer. The first layer includes a first insulator, the second layer includes at least one oxide selected from aluminum oxide, yttrium oxide, lanthanum oxide, gadolinium oxide, ytterbium oxide, hafnium oxide, and zirconium oxide, the third layer includes at least one material selected from silicon, germanium, silicon germanium and silicon carbide, and the third layer is positioned between the semiconductor layer and the insulating layer.
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