公开(公告)号：US09864826B2

公开(公告)日：2018-01-09

申请号：US14644622

申请日：2015-03-11

Applicant: Toshiba Memory Corporation

Inventor： Satoru Fukuchi

IPC: G06F17/50 ,  H05K1/11 ,  H05K1/02 ,  H05K3/00

CPC classification number: G06F17/5068 ,  G06F17/5031 ,  G06F17/5077 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/116 ,  H05K3/0005

Abstract: According to one embodiment, a multilayer printed board includes an insulating substrate, a differential signal wiring, and anti-pad regions. Distances between peripheries of the pad and a constant potential layer in each of the wiring layers are set so that a capacitance between the constant potential layers and a signal via included in a signal line constituting the differential signal wiring, which has a longer route from a transmission end to a reception end, is smaller than a capacitance between the constant potential layers and another signal via included in the other signal line.

公开(公告)号：US10297893B2

公开(公告)日：2019-05-21

申请号：US15448566

申请日：2017-03-02

Applicant: Toshiba Memory Corporation

Inventor： Satoru Fukuchi

IPC: G11C5/06 ,  H01P1/207

Abstract: A circuit includes a conductive layer, an insulation layer on the conductive layer, a transmission line on the insulation layer, the transmission line having a first end and a second end, and a stub on the insulation layer and having a first section of a first constant width connected to the transmission line at a location on the transmission line between the first and second ends, and a second section of a second constant width adjacent to the first section. The first constant width is less than the second constant width.

公开(公告)号：US09911502B2

公开(公告)日：2018-03-06

申请号：US15622191

申请日：2017-06-14

Applicant: Toshiba Memory Corporation

Inventor： Koichi Nagai ,  Katsuya Murakami ,  Shinji Honjo ,  Satoru Fukuchi ,  Akira Tanimoto ,  Isao Ozawa

IPC: G11C16/04 ,  G11C16/30 ,  G11C5/14 ,  G06F13/16

CPC classification number: G11C16/30 ,  G06F13/1668 ,  G11C5/144 ,  Y02D10/14

Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.

公开(公告)号：US10791621B2

公开(公告)日：2020-09-29

申请号：US16590785

申请日：2019-10-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoru Fukuchi

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: A circuit substrate includes an insulating body, a wiring enclosed by the insulating body, a conductive layer formed within the insulating body on a same plane as the wiring, and electrically insulated from the wiring by the insulating body, and one or more conductive vias extending through an edge portion of the conductive layer in a thickness direction intersecting the plane. A first width of the insulating body between the wiring and the conductive layer at a first position in the plane direction that does not correspond to any of said one or more conductive vias is smaller than a second width of the insulating body between the wiring and the conductive layer at a second position in the plane direction that corresponds to one of said one or more conductive vias.

公开(公告)号：US10477674B2

公开(公告)日：2019-11-12

申请号：US15691712

申请日：2017-08-30

Applicant: Toshiba Memory Corporation

Inventor： Satoru Fukuchi

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: A circuit substrate includes an insulating body, a wiring enclosed by the insulating body, a conductive layer formed within the insulating body on a same plane as the wiring, and electrically insulated from the wiring by the insulating body, and one or more conductive vias extending through an edge portion of the conductive layer in a thickness direction intersecting the plane. A first width of the insulating body between the wiring and the conductive layer at a first position in the plane direction that does not correspond to any of said one or more conductive vias is smaller than a second width of the insulating body between the wiring and the conductive layer at a second position in the plane direction that corresponds to one of said one or more conductive vias.

公开(公告)号：US09929712B2

公开(公告)日：2018-03-27

申请号：US15255410

申请日：2016-09-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoru Fukuchi

IPC: H01P3/08 ,  H03H7/42 ,  H01L23/498 ,  H01L23/66 ,  H05K1/02

CPC classification number: H03H7/427 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6661 ,  H01P3/081 ,  H05K1/0245 ,  H05K2201/09272 ,  H05K2201/09727

Abstract: According to one embodiment, there is provided a multilayer substrate including a signal layer. The signal layer includes a first line and a second line which form a differential pair. The first line electrically connects a first node and a second node in the signal layer. The second line electrically connects a third node and a fourth node in the signal layer. The interval between the first line and the second line is approximately constant from the first node to the second node. A physical length from the third node to the fourth node in the second line is shorter than a physical length from the first node to the second node in the first line. A width of the second line is thicker than a width of the first line.